82378ZB Datasheet, PDF (25/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

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82378ZB (SIO) AND 82379 (SIO.A)
3.0. REGISTER DESCRIPTION
The SIO/SIO.A contains PCI configuration Registers and ISA-Compatible Registers. In addition, the SIO.A
contains I/O APIC Registers. Some of the SIO/SIO.A configuration and ISA-Compatible Registers contain
reserved bits. These bits are labeled "Reserved". Software must take care to deal correctly with bit-encoded
fields that are reserved. On reads, software must use appropriate masks to extract the defined bits and not rely
on reserved bits being any particular value. On writes, software must ensure that the values of reserved bit
positions are preserved. That is, the values of reserved bit positions must first be read, merged with the new
values for other bit positions, and the data then written back.
In addition to reserved bits within a register, the SIO/SIO.A contains address locations in the PCI configuration
space that are marked "Reserved" (Table 3). The SIO/SIO.A responds to accesses to these address locations
by completing the PCI cycle. However, reads of reserved address locations yield all zeroes and writes have no
effect on the SIO/SIO.A.
The SIO/SIO.A, upon receiving a hard reset (PCIRST# signal), sets its internal registers to pre-determined
default states. The default values are indicated in the individual register descriptions.
Configuration Registers
The configuration registers (Table 3) are located in PCI configuration space and are only accessible from the
PCI Bus. Addresses for configuration registers are offset values that appear on AD[7:2] and C/BE#[3:0]. The
configuration registers can be accessed as Byte, Word (16-bit), or Dword (32-bit) quantities. All multi-byte
numeric fields use "little-endian" ordering (i.e., lower addresses contain the least significant parts of the fields).
ISA-Compatible Registers
The ISA-Compatible Registers include DMA Registers, Timer Registers, Interrupt Controller Registers, and Non-
Maskable Interrupt and Utility Bus Support Registers (Table 6). All of these registers are accessible from the PCI
Bus. In addition, some of the registers are accessible from the ISA Bus. Except for the BIOS timer Registers, the
ISA-Compatible Registers can only be accessed as byte quantities. If a PCI master attempts a multi-byte access
(i.e., more than one Byte Enable signal asserted), the SIO/SIO.A responds with a target-abort. The BIOS Timer
Register can be accessed as Byte, Word, or Dword quantities.
In general, PCI accesses to the ISA-Compatible Registers will not be broadcast to the ISA Bus. However, PCI
accesses to addresses 70h, 60h, 92h, 3F2h, 372h, and F0h are exceptions. Read and write accesses to these
SIO/SIO.A locations are broadcast onto the ISA Bus. PCI master accesses to SIO/SIO.A Registers will be
retried if the ISA Bus is owned by an ISA master or the DMA controller. Accesses to the BIOS Timer Register
are broadcast to the ISA Bus only if this register is disabled. If this register is enabled, the cycle is not broadcast
to the ISA Bus.
I/O APIC Registers (82379AB Only)
The APIC Registers are indirectly address through two 32-bit registers located in the CPU's memory space—the
I/O Register Select (IOREGSEL) and I/O Window (IOWIN) Registers (Table 1). These registers can be
relocated via the APIC Base Address Relocation Register and are aligned on 128-bit boundaries.
To access an I/O APIC Register, the IOREGSEL Register is written with the address of the intended APIC
Register. Bits[7:0] of the IOREGSEL Register provide the address offset (Table 2). The IOWIN Register then
becomes a 32-bit window pointing to the register selected by the IOREGSEL Register. Note that, for each
redirection table register, there are two offset addresses (e.g., address offset 10h selects IOREDTBL0 bits[31:0]
and 11h selects IOREDTBL0 bits[63:32]).
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