82378ZB Datasheet, PDF (118/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
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Table 10. Decode For System Events To Trigger Fast-Off
Timer Re-load
Address Range
Device
170-17Fh, 1F0-1FFh
IDE/Floppy
278-27Fh
Printer
2E8-2EFh, 2F8-2FFh
COM
320-32Fh
IDE/Floppy
378-37Fh
Printer
3BC-3BFh
Printer
370-377h, 3F0-3F7h
IDE/FLOPPY
3E8-3EFh, 3F8-3FFh
COM
0-0Fh
DMA Registers¹
80-8Fh
DMA Registers¹
C0-DEh
DMA Registers¹
400-43Fh, 481-4FFh
DMA Registers¹
NOTE:
1. Access to positively decoded DMA registers (and aliases) creates a system event.
EXTSMI#
The EXTSMI# input pin provides the system designer the capability to invoke SMM with external hardware. For
example, the EXTSMI# input could be connected to a "green button" permitting the user to enter the Fast-Off
state by depressing a button. The EXTSMI# generation of an SMI is enabled/disabled in the SMIEN Register.
Software Events
Software events (accessing the APMx Registers) indicate that the OS is passing power management
information to the SMI handler. There are two Advanced Power Management (APM) Registers—APM Control
(APMC) and APM Status (APMS) Registers. These registers permit software to generate an SMI; by writing to
the APMC Register. For example, the APMC can be used to pass an APM command between APM OS and
BIOS and the APMS Register could be used to pass data between the OS and the SMI handler.
The two APM Registers are located in normal I/O space. The SIO/SIO.A subtractively decodes PCI accesses to
these registers and forwards the accesses to the ISA Bus. The APM Registers are not accessible by ISA
masters. Note that the remaining power management registers are located in PCI configuration space.
4.11.3. SMI# AND INIT INTERACTION
The SMI# input to the CPU is an edge sensitive signal. When an S-series processor is reset (INIT asserted), the
processor resets the SMI# edge detect logic. After INIT is negated, it takes two clocks before the edge detect
circuit can catch an edge. The SIO/SIO.A only asserts SMI# when INIT is negated. If the SIO/SIO.A asserts
SMI# and then the INIT signal is sampled asserted, the SIO/SIO.A negates SMI#.
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