82378ZB Datasheet, PDF (81/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

E
82378ZB (SIO) AND 82379 (SIO.A)
3.6.1. APMC—ADVANCED POWER MANAGEMENT CONTROL PORT
I/O Address:
Default Value:
Attribute:
0B2h
00h
Read/Write
This register passes data (APM Commands) between the OS and the SMI handler. In addition, writes can
generate an SMI and reads can cause STPCLK# to be asserted. The SIO/SIO.A operation is not affected by the
data in this register.
Bit
Description
7:0 APM Control Port (APMC): Writes to this register store data in the APMC Register and reads return
the last data written. In addition, writes generate an SMI, if bit 7 of the SMIEN Register and
bit 0 of the SMICNTL Register are both is set to 1. Reads cause the STPCLK# signal to be asserted, if
bit 1 of the SMICNTL Register is set to 1. Reads do not generate an SMI.
3.6.2. APMS—ADVANCED POWER MANAGEMENT STATUS PORT
I/O Address:
Default Value:
Attribute:
0B3h
00h
Read/Write
This register passes status information between the OS and the SMI handler. The SIO/SIO.A operation is not
affected by the data in this register.
Bit
Description
7:0 APM Status Port (APMS): Writes store data in this register and reads return the last data written.
3.7. APIC Registers (82379AB Only)
This section describes the registers used to program the Advanced Programmable Interrupt Controller. The I/O
APIC registers are accessed by an indirect addressing scheme using two registers (IOREGSEL and IOWIN)
that are located in the CPU's memory space (memory address specified by the APICBASE Register). To
reference an I/O APIC register, a Dword memory write loads the IOREGSEL Register with a 32 bit value that
specifies the APIC register. The IOWIN Register then becomes a four byte window pointing to the APIC register
specified by bits [7:0] of the IOREGSEL Register. The register address table is at the beginning of the Register
section.
All APIC registers are accessed using 32-bit loads and stores. This implies that to modify a field (e.g., bit, byte)
in any register, the whole 32-bit register must be read, the field modified, and the 32 bits written back. In addition,
registers that are described as 64 bits wide are accessed as multiple independent 32-bit registers.
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