82378ZB Datasheet, PDF (77/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

E
82378ZB (SIO) AND 82379 (SIO.A)
3.5. Control Registers
This section contains NMI Registers, a real-time clock register, Port 92 Register, and the Digital Output Register.
3.5.1. NMISC—NMI STATUS AND CONTROL REGISTER
Address Offset:
Default Value:
Attribute:
061h
00h
Read/Write
This register is used to check the status of different system components, control the output of the speaker
counter (Counter 2), and gate the counter output that drives the SPKR signal.
Bit
Description
7 SERR# Status—RO: 1=SERR# pulsed. 0=No SERR#. Bit 7 is set if a system board agent (PCI
devices or main memory) detects a system board error and pulses the PCI SERR# line. This interrupt is
enabled by setting bit 2 to 0. To reset the interrupt, set bit 2 to 0 and then set it to 1. When writing to
Port 061h, bit 6 must be a 0.
6 IOCHK# NMI Source Status—RO: Bit 6 is set if an expansion board asserts IOCHK# on the ISA/SIO
Bus. This interrupt is enabled by setting bit 3 to 0. To reset the interrupt, set bit 3 to 0 and then set it to
1. When writing to Port 061h, bit 6 must be a 0.
5 Timer Counter 2 OUT Status—RO: The Counter 2 OUT signal state is reflected in bit 5. The value on
this bit following a read is the current state of the Counter 2 OUT signal. Counter 2 must be
programmed following a PCIRST# for this bit to have a determinate value. When writing to Port 061h,
bit 5 must be a 0.
4 Refresh Cycle Toggle—RO: The Refresh Cycle Toggle signal toggles from either 0 to 1 or 1 to 0
following every refresh cycle. This read-only bit is a 0 following PCIRST#. When writing to Port 061h, bit
4 must be a 0.
3 IOCHK# NMI Enable—R/W: 1=Clear and Disable; 0=Enable IOCHK# NMI's.
2 PCI SERR# Enable—R/W: 1=Clear and Disable. 0=Enable.
1 Speaker Data Enable—R/W: 1=SPKR output is 0; 1=SPKR output is the Counter 2 OUT value.
0 Timer Counter 2 Enable—R/W: 0=Disable; 1=Enable
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