82378ZB Datasheet, PDF (87/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

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82378ZB (SIO) AND 82379 (SIO.A)
• 1-to-X Mbytes (up to 16 Mbytes) within which a hole can be opened. Accesses to the hole are not forwarded
to PCI. The top of the region can be programmed on 64 Kbyte boundaries up to 16 Mbytes. The hole can be
between 64 Kbytes and 8 Mbytes in size in 64-Kbyte increments located on any 64-Kbyte boundary.
• Greater than 16 Mbytes are forwarded to PCI
4.1.2. BIOS MEMORY SPACE
PCI Master Access
The SIO/SIO.A supports 512 Kbytes of BIOS space. This includes the normal 128-Kbyte space plus an
additional 384-Kbyte Bios space (known as the enlarged BIOS area). The 128-Kbyte BIOS memory space is
located at 000E0000–000FFFFFh (top of 1 Mbyte), and is aliased at FFFE0000–FFFFFFFFh (top of 4 Gbytes)
and FFEE0000–FFEFFFFFh (top of 4 Gbytes-1 Mbyte). This 128-Kbyte block is split into two 64-Kbyte blocks.
The top 64 Kbytes is always enabled while the bottom 64 Kbytes can be enabled or disabled (the aliases
automatically match). When the lower 64-Kbyte BIOS space (000E0000–000EFFFFh) is enabled, accesses to
this space generate a BIOS chip select (asserts BIOSCS#). Access to the upper 64 Kbytes is controlled by bit 6
in the ISA Clock Divisor Register and bit 4 in the MEMCS# Control Register.
When PCI master accesses to the 128-Kbyte BIOS space at 4 Gbytes - 1 Mbyte are forwarded to the ISA Bus,
the LA20 line is driven to a 1 to avoid aliasing at the 15-Mbyte area. The 4 Gbytes - 1 Mbyte BIOS region
accounts for the condition when A20M# is asserted and an ALT-CTRL-DEL reset is generated. The CPU's reset
vector will access 4 Gbyte - 1 Mbyte. When this gets forwarded to ISA, AD[32:24] are truncated and the access
is aliased to 16 Mbytes - 1 Mbyte = 15 Mbyte space. If ISA memory is present at 15 Mbytes, there will be
contention. Forcing LA20 high aliases this region to 16 Mbytes. The alias here is permissible since this is the
80286 reset vector location.
The additional 384-Kbyte region (FFF80000–FFFDFFFFh) can only be accessed by PCI masters. When
enabled via the UBCSA Register, memory accesses within this region are forwarded to the ISA Bus and
encoded BIOSCS# generated. When forwarded to the ISA Bus, the PCI AD[23:20] signals will be propagated to
the ISA LA[23:20] lines as all 1s which will result in aliasing this 512-Kbyte region at the top of the
16-Mbyte space. To avoid contention, ISA add-in memory must not be present in this space.
All PCI accesses to enabled BIOS space are forwarded to the ISA Bus. Note that PCI burst reads from the BIOS
space invoke "disconnect target termination", in order to meet the PCI incremental latency guidelines.
ISA/DMA Access
ISA masters can only access BIOS in the 000E0000–000FFFFFh region. ISA originated accesses to the
enabled 64-Kbyte sections of the BIOS space (000E0000h–000FFFFFh) generate the encoded BIOSCS#
signal. ISA originated cycles arel not forwarded to the PCI Bus. Encoded BIOSCS# is combinatorially generated
from the ISA SA and LA address bus. Encoded BIOSCS# is disabled during refresh and DMA cycles.
4.1.3. I/O ACCESSES
For PCI master accesses, The SIO/SIO.A positively decodes I/O addresses for registers contained within the
SIO/SIO.A (exceptions: 60h, 70h, 92h, 3F2h, 372h, and F0h). The SIO/SIO.A also provides positive decode for
ISA masters to most of the ISA-Compatible Registers. Refer to the Register Description section for details on
accessing the SIO/SIO.A internal registers. Note that for the SIO.A, the APIC registers are memory mapped and
accesses to these registers are also described in the Register Description section.
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