82378ZB Datasheet, PDF (18/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
E
Signal Name Type
Description
LA[23:17]
I/O
UNLATCHED ADDRESS: These address lines allow accesses to physical memory
on the ISA Bus up to 16 Mbytes. The LA[23:17] signals are at an unknown state
upon reset.
For the 82378ZB, these signals are undefined during DMA type "A", "B", and "F"
cycles.
SA[19:0]
I/O
SYSTEM ADDRESS BUS: These bi-directional address lines define the selection
with the granularity of one byte within the one Mbyte section of memory defined by
the LA[23:17] address lines. The address lines SA[19:17] that are coincident with
LA[19:17] are defined to have the same values as LA[19:17] for all memory cycles.
For I/O accesses, only SA[15:0] are used. SA[19:0] are outputs when the
SIO/SIO.A owns the ISA Bus. SA[19:0] are inputs when an external ISA Master
owns the ISA Bus. SA[19:0] are at an unknown state upon reset.
For the 82378ZB, SA[19:0] are undefined during DMA type "A", "B", or "F" cycles.
SBHE#
I/O
SYSTEM BYTE HIGH ENABLE: SBHE# indicates, when asserted, that a byte is
being transferred on the upper byte (SD[15:8]) of the data bus. SBHE# is negated
during refresh cycles. SBHE# is at an unknown state upon reset.
MEMCS16# OD
MEMORY CHIP SELECT 16: MEMCS16# is a decode of LA[23:17] without any
qualification of the command signal lines. ISA slaves that are 16-bit memory devices
drive this signal low. The SIO/SIO.A drives this signal low during ISA master to PCI
memory cycles. MEMCS16# is at an unknown state upon reset.
MASTER#
I
(82378ZB
Only)
MASTER: An ISA Bus master asserts MASTER# to indicate that it has control of
the ISA Bus. Before the ISA master can assert MASTER#, it must first sample
DACK# active. Once MASTER# is asserted, the ISA master has control of the ISA
Bus until it negates MASTER#.
MEMR#
I/O
MEMORY READ: MEMR# is the command to a memory slave that it may drive
data onto the ISA data bus. MEMR# is an output when the SIO/SIO.A is a master
on the ISA Bus. MEMR# is an input when an ISA master, other than the SIO/SIO.A,
owns the ISA Bus. This signal is also driven by the SIO/SIO.A during refresh
cycles.
For compatible timing mode DMA cycles, the SIO/SIO.A, as a master, asserts
MEMR# if the address is less than 16 Mbytes. This signal is not generated for
accesses to addresses greater than 16 Mbytes.
For the 82378ZB, MEMR# is not driven active during DMA type "A", "B", or "F"
cycles.
MEMW#
I/O
MEMORY WRITE: MEMW# is the command to a memory slave that it may latch
data from the ISA data bus. MEMW# is an output when the SIO/SIO.A owns the ISA
Bus. MEMW# is an input when an ISA master, other than the SIO/SIO.A, owns the
ISA Bus.
For compatible timing mode DMA cycles, the SIO/SIO.A, as a master, asserts
MEMW# if the address is less than 16 Mbytes. This signal is not generated for
accesses to addresses greater than 16 Mbytes.
For the 82378ZB, MEMW# is not driven active during DMA type "A", "B", or "F"
cycles.
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