82378ZB Datasheet, PDF (64/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
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3.2.13. DMC—DMA MASTER CLEAR REGISTER
Address Offset:
Default Value:
Attribute:
Channel 0−3—00Dh; Channel 4−7—0DAh
All bits undefined
Write Only
This software instruction has the same effect as the hardware Reset. The Command, Status, Request, and
Internal First/Last Flip-Flop registers are cleared and the Mask Register is set. The DMA controller enters the
idle cycle.
Bit
Description
7:0 Master Clear: No specific pattern. Command enabled with a write to the I/O port address.
3.2.14. DCM—DMA CLEAR MASK REGISTER
Address Offset:
Default Value:
Attribute:
Channel 0−3—00Eh; Channel 4−7—0DCh
All bits undefined
Write Only
This command clears the mask bits of all four channels, enabling them to accept DMA requests. I/O port 0Eh is
used for Channels 0-3 and I/O port 0DCh is used for Channels 4-7.
Bit
Description
7:0 Clear Mask Register: No specific pattern. Command enabled with a write to the I/O port address.
3.2.15. SCATTER/GATHER (S/G) COMMAND REGISTER (82378ZB Only)
Address Offset:
Default Value:
Attribute:
Channels 0 default address0410h;
Channels 1 default address0411h;
Channels 2 default address0412h;
Channels 3 default address0413h;
00h
Write Only, Relocatable
Channels 5 default address0415h
Channels 6 default address0416h
Channels 7 default address0417h
The S/G Command Register controls operation of the descriptor table aspect of scatter/gather transfers. This
register can be used to start and stop a scatter/gather transfer. The register can also be used to select between
IRQ13 and EOP to be asserted following a terminal count. The current scatter/gather transfer status can be read
in the scatter/gather channel's corresponding S/G Status Register. After a PCIRST# or Master Clear, IRQ13 is
disabled and EOP is enabled.
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