82378ZB Datasheet, PDF (88/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
E
4.1.4. SUBTRACTIVELY DECODED CYCLES TO ISA
The addresses that reside on the ISA Bus could be highly fragmented. For this reason, subtractive decoding is
used to forward PCI cycles to the ISA Bus. An inactive DEVSEL# will cause the SIO/SIO.A to forward the PCI
cycle to the ISA Bus. The DEVSEL# sample point can be configured for three different settings—fast, typical, or
slow. Note that when unclaimed cycles are forwarded to the ISA Bus, the SIO/SIO.A asserts DEVSEL#.
Since an active MEMCS# will always result in an active DEVSEL# at the "Slow" sample point, MEMCS# is used
as an early indication of DEVSEL#. In this case, if the device using MEMCS# is the only "slow" agent in the
system, the sample point can be moved in to the "typical" edge.
Unclaimed PCI cycles with memory addresses above 16M and I/O addresses above 64K are not forwarded to
the ISA Bus. To avoid the possibility of aliasing, the SIO/SIO.A does not respond with DEVSEL# (BIOS
accesses are an exception to this).
4.1.5. UTILITY BUS ENCODED CHIP SELECTS
The SIO/SIO.A generates encoded chip selects for certain functions that are located on the utility bus (formerly
X-Bus). The encoded chip selects are generated combinatorially from the ISA SA[15:0] address bus. Chip
selects can be enabled or disabled via configuration registers. In general, the chip select addresses do not
reside in the SIO/SIO.A itself. Write only addresses 70h, 372h, 3F2h are exceptions since particular bits from
these registers reside in the SIO/SIO.A. For ISA master cycles, the SIO/SIO.A responds to writes to address
70h, 372h, and 3F2h by generating IOCHRDY and writing to the appropriate bits.
Note that the SIO/SIO.A monitors read accesses to address 60h to support the mouse function. In this case,
IOCHRDY is not generated.
4.2. PCI Interface
4.2.1. PCI COMMAND SET
Bus commands indicate to the slave the type of transaction the master is requesting. Bus Commands are
encoded on the C/BE[3:0]# lines during the address phase of a PCI cycle.
C/BE[3:0]#
Table 6. PCI Commands
Command Type As Slave
Supported As Slave Supported As Master
0000
Interrupt Acknowledge
Yes
No
0001
Special Cycle⁴
No/Yes
No
0010
I/O Read
Yes
No
0011
I/O Write
Yes
No
0100
Reserved³
No
No
0101
Reserved³
No
No
0110
Memory Read
Yes
Yes
0111
Memory Write
Yes
Yes
1000
Reserved³
No
No
88