82378ZB Datasheet, PDF (97/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

E
82378ZB (SIO) AND 82379 (SIO.A)
The DMA controller will terminate a S/G cycle by detecting an End of List (EOL) bit in the SGD Table. After the
EOL bit is detected, the channel transfers the buffers in the Base and Current register sets, if they are loaded. At
terminal count the channel asserts EOP or IRQ13, depending on its programming and set the terminate bit in the
S/G Status Register. If the channel asserted IRQ13, then the appropriate bit is set in the S/G Interrupt Status
Register. The active bit in the S/G Status Register will be reset and the channel's Mask bit will be set.
S GD Table Ptr. Register
SGD TABLE
Ptr.
SGD A
Ptr. + 8h
SGD B
P tr. + 10h
SGD C
Memory Address
0
Transfer Size
Memory Address
0
Transfer Size
Memory Address
1
Transfer Size
MEMORY BUFFERS
Buffer A
Buffer C
Figure 4. Link List Example
Buffer B
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