82378ZB Datasheet, PDF (45/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

E
82378ZB (SIO) AND 82379 (SIO.A)
3.1.20. UBCSA—UTILITY BUS CHIP SELECT A REGISTER
Address Offset:
Default Value:
Attribute:
4Eh
07h
Read/Write
This register enables/disables accesses to the RTC, keyboard controller, floppy disk controller, IDE, and BIOS
locations E0000–EFFFFh and FFF80000–FFFDFFFFh. Disabling any of these bits prevents the encoded chip
select bits (ECSADDR[2:0]) and Utility Bus transceiver control signal (UBUSOE#) for that device from being
generated.
This register is also used to select which address range (primary or secondary) will be decoded for the resident
floppy controller and IDE. This ensures that there is no contention with the Utility Bus transceiver driving the
system data bus during read accesses to these devices.
Bit
Description
7 Extended BIOS Enable: When bit 7=1 (enabled), PCI accesses to locations FFF80000–FFFDFFFFh
result in the generation of the encoded signals (ECSADDR[2:0]) for BIOS. When enabled, PCI master
accesses to this area are positively decoded and UBUSOE# is generated. When this bit is disabled (bit
7=0), the SIO/SIO.A does not generate the encoded (ECSADDR[2:0]) signals or UBUSOE#.
6 Lower BIOS Enable: When bit 6=1 (enabled), PCI or ISA accesses to the lower 64 Kbyte BIOS block
(E0000–EFFFFh) at the top of 1 Mbyte, or the aliases at the top of 4 Gbyte and 4 Gbyte -
1 Mbyte results in the generation of the encoded (ECSADDR[2:0]) signals for BIOS. When enabled,
PCI master accesses to this area are positively decoded to the ISA Bus, unless bit 4 in the MEMCS#
Control Register is set to a 1 in which case these regions are subtractively decoded. Also, when
enabled, ISA master or DMA master accesses to this region are not forwarded to the PCI Bus. When
this bit is disabled (bit 6=0), the SIO/SIO.A does not generate the encoded (ECSADDR[2:0]) signals.
Also, when this bit is disabled, ISA master or DMA accesses to this region are forwarded to PCI, if bit 3
in the IADCON Register is set to 1.
4 IDE Decode Enable: Bit 4 enables/disables IDE locations 1F0–1F7h (primary) or 170–177h
(secondary) and 3F6h, 3F7h (primary) or 376h, 377h (secondary). When bit 4=1, the IDE encoded chip
select signals and the Utility Bus transceiver signal (UBUSOE# ) are generated for these addresses.
When bit 4=0, these signals are not generated for these addresses.
5,3:2
Floppy Disk Address Locations Enable: Bits 2 and 3 are used to enable or disable the floppy
locations as indicated below. A PCIRST# sets bit 2 to 1 and bit 3 to 0. Bit 5 is used to select between
the primary and secondary address range used by the floppy controller and the IDE. Only primary or
only secondary can be programmed at any one time. A PCIRST# sets this bit to 0 (primary). The
following table shows how these bits are used to select the floppy controller:
Address
X
3F0h, 3F1h
3F2–3F7h
370h, 371h
372–37Fh
Bit 5
X
0
0
1
1
Bit 3
X
1
X
1
X
Bit 2
X
X
1
X
1
DSKCHG
0
1
1
1
1
ECSADDR[2:0]
111
100
100
100
100
FLOPPYCS#
1
0
0 (note)
0
0 (note)
NOTE
If IDE decode is enabled (bit 4=1), all accesses to locations 03F6h and 03F7h (primary) or 0376h and 0377h
(secondary) result in the ECSADDR[2:0] signals generating a decode for IDECS1# (FLOPPYCS# is not
generated). An external AND gate can be used to tie IDECS1# and FLOPPYCS# together to insure that the
floppy is enabled for these accesses. If IDE decode is disabled (bit 4=0), and the decode for the floppy is
enabled, then the encoded chip selects for the floppy locations are generated.
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