82378ZB Datasheet, PDF (60/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
E
3.2.6. MASK REGISTER—WRITE ALL MASK BITS
Address Offset:
Default Value:
Attribute:
Channels 0−3—0Fh; Channels 4−7—0DEh
Bit[3:0]=1, Bit[7:4]=0
Read/Write
A channel's mask bit is automatically set to 1 when the Current Byte/Word Count Register reaches terminal
count (unless the channel is programmed for autoinitialization). Bits[3:0] are set to 1 by a PCIRST# or a Master
Clear. Setting bits[3:0] to 1 disables all DMA requests until a clear mask register instruction enables the
requests. Note that, masking DMA channel 4 (DMA controller 2, channel 0) will automatically mask DMA
channels [3:0]. In addition, masking DMA controller 2 with a write to Port 0DEh will also mask DREQ assertions
from DMA controller 1.
Bit
Description
7:4 Reserved: Must be 0.
3:0 Channel Mask Bits: 1=Disable the corresponding DREQ(s); 0=Enable the corresponding DREQ(s).
Bit
Channel
0
0 (4)
1
1 (5)
Bit
Channel
2
2 (6)
3
3 (7)
3.2.7. DS—DMA STATUS REGISTER
Address Offset:
Default Value:
Attribute:
Channels 0−3—08h; Channels 4−7—0D0h
00h
Read Only
Each DMA controller has a read-only DMA Status Register indicating which channels have reached terminal
count and which channels have a pending DMA request.
Bit
Description
7:4 Channel Request Status: When a valid DMA request is pending for a channel (on its DREQ signal
line), the corresponding bit is set to 1. When a DMA request is not pending for a particular channel, the
corresponding bit is set to 0. The source of the DREQ may be hardware, a timed-out block transfer, or a
software request. Note that channel 4 does not have DREQ or DACK lines, so the response for a read
of DMA2 status for channel 4 is irrelevant.
Bit
Channel
4
0
5
1 (5)
Bit
Channel
6
2 (6)
7
3 (7)
3:0 Channel Terminal Count Status: 1=TC reached; 0=TC is not reached.
Bit
Channel
0
0
1
1 (5)
Bit
Channel
2
2 (6)
3
3 (7)
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