82378ZB Datasheet, PDF (6/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
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4.5.1. DMA TIMINGS ................................ ................................ ................................ ................................ ....94
4.5.1.1. COMPATIBLE TIMING (82378ZB AND 82379AB) ................................ ................................ ...95
4.5.1.2. TYPE "A" TIMING (82378ZB) ................................ ................................ ................................ .....95
4.5.1.3. TYPE "B" TIMING (82378ZB) ................................ ................................ ................................ .....95
4.5.1.4. TYPE "F" TIMING (82378ZB) ................................ ................................ ................................ .....95
4.5.1.5. DREQ AND DACK# LATENCY CONTROL (82378ZB AND 82379AB) ................................ ..95
4.5.2. ISA REFRESH CYCLES (82378ZB and 82379AB) ................................ ................................ ......... 95
4.5.3. SCATTER/GATHER (S/G) DESCRIPTION (82378ZB) ................................ ................................ ...95
4.6. DATA BUFFERING ................................ ................................ ................................ ................................ ...98
4.6.1. DMA/ISA MASTER LINE BUFFER ................................ ................................ ................................ ...98
4.6.2. PCI MASTER POSTED WRITE BUFFER ................................ ................................ ........................ 98
4.7. SIO TIMERS ................................ ................................ ................................ ................................ ............... 98
4.7.1. INTERVAL TIMERS ................................ ................................ ................................ ........................... 98
4.7.2. BIOS TIMER ................................ ................................ ................................ ................................ ........ 99
4.8. INTERRUPT CONTROLLER ................................ ................................ ................................ .................. 100
4.8.1. EDGE AND LEVEL TRIGGERED MODES ................................ ................................ .................... 101
4.8.2. NON-MASKABLE INTERRUPT (NMI) ................................ ................................ ............................ 101
4.9. ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC) (82379AB ONLY) ............... 102
4.9.1. PHYSICAL CHARACTERISTICS OF APIC BUS (82379AB Only) ................................ .............. 105
4.9.2. ARBITRATION FOR APIC BUS (82379AB Only) ................................ ................................ ..........105
4.9.3. INTR AND THE PENTIUM ^® PROCESSOR’S "THROUGH LOCAL MODE" (82379AB Only) ....105
4.9.4. PULSING OF APICD1 DURING CPU RESET (82379AB Only) ................................ ................... 107
4.9.5. SIO.A ASSERTING SIGNALS LOW DURING PCIRST# (82379AB ONLY) ................................ 111
4.10. UTILITY BUS PERIPHERAL SUPPORT ................................ ................................ ............................. 111
4.11. POWER MANAGEMENT ................................ ................................ ................................ ...................... 116
4.11.1. SMM MODE ................................ ................................ ................................ ................................ ....117
4.11.2. SMI SOURCES ................................ ................................ ................................ ............................... 117
4.11.3. SMI# AND INIT INTERACTION ................................ ................................ ................................ ....118
4.11.4. CLOCK CONTROL ................................ ................................ ................................ ......................... 119
4.11.5. DUAL-PROCESSOR POWER MANAGEMENT SUPPORT (82379AB Only) ........................... 120
4.11.5.1. SMI# DELIVERY MECHANISM ................................ ................................ ............................. 120
4.11.5.2. STPCLK# TIED TO BOTH SOCKETS ................................ ................................ ................... 120
4.11.5.3. SMI#/INTR (APIC MODE) ................................ ................................ ................................ .......121
4.11.6. INTERRUPT LEVELS AND SYSTEM EVENT GENERATION IN POWER MANAGED
SYSTEMS (82378ZB Only) ................................ ................................ ................................ .................... 121
4.12. DESIGN CONSIDERATIONS (82378ZB/82379AB) ................................ ................................ ........... 121
4.12.1. Good Layout Practice ................................ ................................ ................................ ..................... 121
4.12.2. ASYNCHRONOUSLY SWITCHING SIGNALS ................................ ................................ ............ 121
5.0. ELECTRICAL CHARACTERISTICS.........................................................................................................122
5.1. MAXIMUM RATINGS ................................ ................................ ................................ .............................. 122
6.0. PIN ASSIGNMENT......................................................................................................................................123
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