82378ZB Datasheet, PDF (44/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
E
3.1.19. ICD—ISA CLOCK DIVISOR REGISTER
Address Offset:
Default Value:
Attribute:
4Dh
40h
Read/Write
This register selects the integer value used to divide the PCI clock (PCICLK) to generate the ISA clock
(SYSCLK). In addition, this register provides an ISA Reset bit to software control RSTDRV, a bit to
enable/disable the MOUSE function, a bit to enable/disable the coprocessor error support, and a bit to disable
the positive decode for the upper 64 Kbytes of BIOS at the top of 1 Mbyte (F0000–FFFFFh) and aliased regions.
Bit
Description
7 Reserved: Read as 0.
6 Positive Decode of Upper 64 Kbyte BIOS Enable: This bit enables (bit 6=1) and disables (bit 6=0)
the positive decode of the upper 64 Kbytes of BIOS area at the top of 1 Mbyte (F0000–FFFFFh) and the
aliased regions at the top of 4 Gbytes (FFFF0000–FFFFFFFFh) and 4 Gbytes-1 Mbyte (FFEF0000–
FFEFFFFFh). When bit 6=1, these address regions are positively decoded, unless bit 4 in the MEMCS#
Control Register is set to a 1 in which case these regions are subtractively decoded. When bit 6=0,
these address regions are subtractively decoded. The encoded chip selects for BIOSCS# and the
UBUSOE# signal will always be generated when these locations are accessed, regardless of the state
of this bit.
5 Coprocessor Error Enable: This bit is used to enable and disable the Coprocessor error support.
When enabled (bit 5=1), the FERR# input, when driven active, triggers an IRQ13 to the SIO/SIO.A
interrupt controller. FERR# is also used to gate the IGNNE# output. When disabled (bit 5=0), the
FERR# signal can be used as IRQ13 and the coprocessor support is disabled.
4 IRQ12/M Mouse Function Enable: When this bit is set to 1, IRQ12/M provides the mouse function.
When this bit is set to 0, IRQ12/M provides the standard IRQ12 interrupt function.
3 RSTDRV Enable: This bit is used to enable RSTDRV on the ISA Bus. When this bit is set to 1,
RSTDRV is asserted and remains asserted until this bit is set to a 0. When set to 0, normal operation of
RSTDRV is provided. This bit should be used during configuration to reset the ISA Bus when changing
the clock divisor. Note that the software must ensure that RSTDRV is asserted for a minimum of 1 µs.
2:0 PCICLK-to-ISA SYSCLK Divisor: These bits are used to select the integer that is used to divide the
PCICLK down to generate the ISA SYSCLK. Upon reset, these bits are set to 000 (divisor of 4
selected). For PCI frequencies less than 33 MHz (not including 25 MHz), a clock divisor value must be
selected that ensures that the ISA Bus frequency does not violate the 6 MHz to 8.33 MHz SYSCLK
specification.
Bit[2:0]
000
001
010
011
Divisor
4 (33 MHz)
3 (25 MHz)
Reserved
Reserved
SYSCLK
8.33 MHz
8.33 MHz
Bit[2:0]
100
101
110
111
Divisor
Reserved
Reserved
Reserved
Reserved
SYSCLK
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