82378ZB Datasheet, PDF (53/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

E
82378ZB (SIO) AND 82379 (SIO.A)
NOTE
Before writing to the FTMR Register, the Fast-Off Timer must be stopped via bit 3 of the SMICNTL
Register. In addition, this register should NOT be programmed to 00h.
Bit
Description
7:0 Fast-Off Timer Value: Bits[7:0] contain the starting count value. A read from the FTMR Register
returns the value last written.
3.1.33. SMIREQ—SMI REQUEST REGISTER
Address Offset:
Default Value:
Attribute:
AA−ABh
00h
Read/Write
The SMIREQ Register contains status bits indicating the cause of an SMI. When an enabled event causes an
SMI, the SIO/SIO.A automatically sets the corresponding event's status bit to 1. Note that, if software attempts to
set a status bit to 0 at the same time that the SIO/SIO.A is setting it to 1, the bit is set to 1. If the SMI event is still
active when the corresponding SMIREQ bit is set to 0, the SIO/SIO.A does not set the status bit back to a 1 (i.e.,
there is only one status indication per active SMI event).
When an IRQx signal is asserted, the corresponding RIRQx bit is set to a 1. If the IRQx signal is still active when
software sets the RIRQx bit to 0, RIRQx is not set back to a 1. The IRQx may be negated before software sets
the RIRQx bit to 0. If the RIRQx bit is set to 0 at the same time a new IRQx is activated, RIRQx remains at 1.
This indicates to the SMI handler that a new SMI event has been detected.
NOTE
1. The SMIREQ bits are set, cleared, or read independently of each other and independently of the
CSMIGATE bit in the SMICNTL Register.
2. If an IRQx is set in level mode and shared by two devices, the IRQ should not be enabled as an
SMI# event. The SIO/SIO.A SMIREQ bits are essentially set with an edge. When the second IRQ
occurs on a shared IRQ, there is no second edge and the SMI# will not be generated for the
second IRQ.
Bit
Description
15:8 Reserved
7 APM SMI Status (RAPMC): The SIO/SIO.A sets this bit to 1 to indicate that a write to the APM
Control Register caused an SMI. Software sets this bit to a 0 by writing a 0 to it.
6 EXTSMI# SMI Status (REXT): The SIO/SIO.A sets this bit to 1 to indicate that EXTSMI# caused an
SMI. Software sets this bit to a 0 by writing a 0 to it.
5 Fast-Off Timer Expired Status (RFOT): The SIO/SIO.A sets this bit to 1 to indicate that the Fast-Off
Timer expired and caused an SMI. Software sets this bit to a 0 by writing a 0 to it. When the Fast-Off
Timer expires, the SIO/SIO.A sets this bit to a 1. Note that the timer re-starts counting one the next
clock after it expires.
4 IRQ12 Request SMI Status (RIRQ12): The SIO/SIO.A sets this bit to 1 to indicate that IRQ12 caused
an SMI. Software sets this bit to a 0 by writing a 0 to it.
3 IRQ8# Request SMI Status: The SIO/SIO.A sets this bit to 1 to indicate that IRQ8# caused an SMI.
Software sets this bit to a 0 by writing a 0 to it.
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