82378ZB Datasheet, PDF (70/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
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The count must be read according to the programmed format. Specifically, if the Counter is programmed for two
byte counts, two bytes must be read. The two bytes do not have to be read one right after the other (read, write,
or programming operations for other counters may be inserted between the reads).
NOTE
1. If a counter is programmed to read/wr ite two-byte counts, a program must not transfer control
between reading the first and second byte to another routine that also reads from that same
counter. Otherwise, an incorrect count will be read. Finish reading the latched two-byte count
before transferring control to another routine.
2. The Timer Counter Register bit definitions are different during the Counter Latch Command than
for a normal Timer Counter Register write.
Bit
Description
7:6 Counter Selection: Bits 6 and 7 are used to select the counter for latching.
Bit[7:6]
00
01
Function
latch counter 0 select
latch counter 1 select
Bit[7:6]
10
11
Function
latch counter 2 select
Read Back Command select
5:4 Counter Latch Command: When bits[5:4]=00, the Counter Latch Command is selected during a write
to the Timer Control Word Register. Following the Counter Latch Command, I/O reads from the
selected counter's I/O addresses produce the current latched count.
3:0 Reserved. Must be 0.
3.3.2. INTERVAL TIMER STATUS BYTE FORMAT REGISTER
Address Offset:
Default Value:
Attribute:
Counter 0—040h; Counter 1—041h; Counter 2—042h
Bits[6:0]=X, Bit 7=0
Read Only
Each counter's status byte can be read following an Interval Timer Read Back Command. If latch status is
chosen (bit 4=0, Read Back Command) as a read back option for a given counter, the next read from the
counter's Counter Access Ports Register returns the status byte.
Bit
Description
7 Counter OUT Pin State: 1=Pin is 1; 0=Pin is 0.
6 Count Register Status: This bit indicates when the last count written to the Count Register (CR) has
been loaded into the counting element (CE). 0=Count has been transferred from CR to CE and is
available for reading. 1=Count has not been transferred from CR to CE and is not yet available for
reading.
5:4 Read/Write Selection Status: Bits[5:4] reflect the read/write selection made through bits[5:4] of the
control register. The binary codes returned during the status read match the codes used to program the
counter read/write selection.
Bit[5:4]
00
01
Function
Bit[5:4]
Counter Latch Command
10
R/W Least Significant Byte 11
Function
R/W Most Significant Byte
R/W LSB then MSB
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