82378ZB Datasheet, PDF (100/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
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A write operation to the BIOS Timer Register will initiate the counting sequence. The timer can be initiated by
writing either the 16-bit data portion or the whole 32-bit register (upper 16 bits are "don't care"). After initialization,
the BIOS timer will start decrementing until it reaches zero. Then it will stop decrementing (and hold a zero
value) until initialized again.
After the timer is initialized, the current value can be read at any time and the timer can be reprogrammed (new
initial value written), even before it reaches zero.
All write and read operations to the BIOS timer Register should include all 16 counter bits. Separate accesses to
the individual bytes of the counter must be avoided since this can cause unexpected results (wrong count
intervals).
4.8. Interrupt Controller
The SIO/SIO.A provides an ISA-compatible interrupt controller which incorporates the functionality of two 82C59
interrupt controllers. The two controllers are cascaded so that 14 external and two internal interrupts are
possible. The master interrupt controller provides IRQ[7:0] and the slave interrupt controller provides IRQ[15:8]
(see Figure 5). The two internal interrupts are used for internal functions only and are not available to the user.
IRQ2 is used to cascade the two controllers together and IRQ0 is used as a system timer interrupt and is tied to
Interval Timer 1, Counter 0. The remaining 14 interrupt lines (IRQ1, IRQ[15:3]) are available for external system
interrupts. Edge or level sense selection is programmable on a by-controller basis.
The Interrupt Controller consists of two separate 82C59 cores. Interrupt Controller 1 (CNTRL-1) and Interrupt
Controller 2 (CNTRL-2) are initialized separately and can be programmed to operate in different modes. The
default settings are: 80x86 Mode, Edge Sensitive (IRQ0-15) Detection, Normal EOI, Non-Buffered Mode,
Special Fully Nested Mode disabled, and Cascade Mode. CNTRL-1 is connected as the Master Interrupt
Controller and CNTRL-2 is connected as the Slave Interrupt Controller.
Note that IRQ13 is generated internally (as part of the coprocessor error support) by the SIO/SIO.A when bit 5 in
the ISA Clock Divisor Register is set to a 1. When this bit is set to a 0, then the FERR#/IRQ13 signal is used as
an external IRQ13 signal and has the same functionality as the normal IRQ13 signal. IRQ12/M is generated
internally (as part of the mouse support) by the SIO/SIO.A when bit 4 in the ISA Clock Divisor Register is set to
a 1. When set to a 0, the standard IRQ12 function is provided.
IRQ8#
IRQ9
IRQ10
IRQ11
IRQ12/Mouse
FERR#
IRQ14
IRQ15
0# _82C59
1
2
Core
3
4 ^{Controller 2}
5
6 (Slave)
7
Timer 1
Counter 0
INTR
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
0
1
2
82C59
Core
3
4 ^{Controller 1}
5
6 (Master)
7
INT
(To CPU)
057105
Figure 5. Block Diagram of the Interrupt Controller
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