82378ZB Datasheet, PDF (101/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

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82378ZB (SIO) AND 82379 (SIO.A)
4.8.1. EDGE AND LEVEL TRIGGERED MODES
There are two ELCR Registers, one for each 82C59 bank. They are located at I/O ports 04D0h (for the Master
Bank, IRQ[7:3,1:0]#) and 04D1h (for the Slave Bank, IRQ[15:8])#. They allow the edge and level sense selection
to be made on an interrupt by interrupt basis instead of on a complete bank. Interrupts reserved for ISA use
MUST be programmed for edge sensitivity (to ensure ISA compatibility). That is, IRQ (0,1,2,8#,13) must be
programmed for edge sensitive operation. The LTIM bit (Edge/Level Bank select, offsets 20h, A0h) is disabled in
the SIO/SIO.A. The default programming is equivalent to programming the LTIM bit (ICW1 bit 3) to a 0.
If an ELCR bit is equal to 0, an interrupt request will be recognized by a low to high transition on the
corresponding IRQ input. The IRQ input can remain high without generating another interrupt.
If an ELCR bit is equal to 1, an interrupt request will be recognized by a "low" level on the corresponding IRQ
input, and there is no need for an edge detection. For level triggered interrupt mode, the interrupt request signal
must be removed before the EOI command is issued or the CPU interrupt must be disabled. This is necessary to
prevent a second interrupt from occurring.
In both the edge and level triggered modes the IRQ inputs must remain active until after the falling edge of the
first INTA#. If the IRQ input goes inactive before this time a DEFAULT IRQ7 will occur when the CPU
acknowledges the interrupt. This can be a useful safeguard for detecting interrupts caused by spurious noise
glitches on the IRQ inputs. To implement this feature the IRQ7 routine is used for "clean up" simply executing a
return instruction, thus ignoring the interrupt. If IRQ7 is needed for other purposes a default IRQ7 can still be
detected by reading the ISR. A normal IRQ7 interrupt will set the corresponding ISR bit, a default IRQ7 won't. If a
default IRQ7 routine occurs during a normal IRQ7 routine, however, the ISR will remain set. In this case, it is
necessary to keep track of whether or not the IRQ7 routine was previously entered. If another IRQ7 occurs, it is
a default.
4.8.2. NON-MASKABLE INTERRUPT (NMI)
An NMI is an interrupt requiring immediate attention and has priority over the normal interrupt lines (IRQx). The
SIO/SIO.A indicates error conditions by generating a non-maskable interrupt. NMI interrupts are caused by:
1. System Errors on the PCI Bus. SERR# is driven low by a PCI resource when this error occurs.
2. Parity errors on the add-in memory boards on the ISA expansion bus. IOCHK# is driven low when this error
occurs.
The NMI logic incorporates two different 8-bit registers—the NMI Status and Control Register and the NMI
Enable and Real-Time Clock Address Register. These registers are described in the Register Description
Section.
All NMI sources can be enabled or disabled by setting Port 070h bit 7 to a 0 or 1. This disable function does not
clear the NMI detect flip-flops. This means, if NMI is disabled then enabled via Port 070h, then an NMI will occur
when Port 070h is re-enabled if one of the NMI detect flip-flops had been previously set.
To ensure that all NMI requests are serviced, the NMI service routine software needs to incorporate a few very
specific requirements. These requirements are due to the edge detect circuitry of the host microprocessor,
80386 or 80486. The software flow would need to be the following:
1. NMI is detected by the processor on the rising edge of the NMI input.
2. The processor will read the status stored in Port 061h to determine what sources caused the NMI. The
processor may then set to 0 the register bits controlling the sources that it has determined to be active.
Between the time the processor reads the NMI sources and sets them to a 0, an NMI may have been
generated by another source. The level of NMI will then remain active. This new NMI source will not be
recognized by the processor because there was no edge on NMI.
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