82378ZB Datasheet, PDF (65/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

E
82378ZB (SIO) AND 82379 (SIO.A)
Bit
Description
7 IRQ13/EOP Select. Bit 7, if enabled via bit 6 of this register, selects whether EOP or IRQ13 is
asserted at termination caused by a last buffer expiring. The last buffer can be either the last buffer in
the list or the last buffer loaded in the DMA while it is suspended. If bit 7=1 (and bit 6=1), EOP is
asserted when the last buffer is completed. If bit 7=0 (and bit 6=1), IRQ13 is asserted when the last
buffer is completed.
EOP can be used to alert an expansion bus I/O device that a scatter/gather termination condition was
reached. The I/O device, in turn, can assert its own interrupt request line to invoke a dedicated interrupt
handling routine. IRQ13 should be used when the CPU needs to be notified directly.
Following PCIRST#, or Master Clear, the value stored for this bit is 1, and EOP is selected. Bit 6 must
be set to a 1 to enable this bit during a S/G Command register write. When bit 6 is a 0 during the write,
bit 7 will not have any effect on the current EOP/IRQ13 selection.
6 IRQ13/EOP Programming Enable. Enabling IRQ13/EOP programming allows initialization or
modification of the S/G termination handling bits. When bit 6=0, bit 7 does not affect the state of IRQ13
or EOP assertion. When bit 6=1, bit 7 determines the termination handling following a terminal count.
5:2 Reserved. Must be 0.
1:0 Scatter/Gather (S/G) Commands. This 2-bit field is used to start and stop scatter/gather.
Bits[1:0]=00: No S/G operation
No S/G command operation is performed. Bits[7:6] may still be used to program IRQ13/EOP selection.
Bits[1:0]=01: Start S/G Command
The Start command initiates the scatter/gather process. Immediately after the start command is issued
(setting bits[1:0] to 01), a request is issued to fetch the initial buffer from the descriptor table to fill the
Base Register set in preparation for performing a transfer. The buffer prefetch request has the same
priority with respect to other channels as the DREQ it is associated with. Within the channel, DREQ is
higher in priority than a prefetch request.
The Start command assumes the Base and Current Registers are both empty and will request a
prefetch automatically. Note that this command also sets the S/G Status Register to S/G Active, Base
Empty, Current Empty, not Terminated, and Next Null Indicator to 0. The EOP/IRQ13 bit will still reflect
the last value programmed
Bits[1:0]=10: Stop S/G Command
The Stop command halts a S/G transfer immediately. When a Stop command is given, the Terminate bit
in the S/G Status Register and the DMA channel mask bit are both set.
Bits[1:0]=11: Reserved
3.2.16. SCATTER/GATHER (S/G) STATUS REGISTER (82378ZB Only)
Address Offset:
Default Value:
Attribute:
Channels 0 default address0418h;
Channels 1 default address0419h;
Channels 2 default address041Ah;
Channels 3 default address041Bh;
00h
Read Only, Relocatable
Channels 5 default address041Dh
Channels 6 default address041Eh
Channels 7 default address041Fh
65