82378ZB Datasheet, PDF (111/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

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82378ZB (SIO) AND 82379 (SIO.A)
4.9.5. SIO.A ASSERTING SIGNALS LOW DURING PCIRST# (82379AB ONLY)
The SIO.A drives SMI#, ALT_A20, INT, NMI, IGNNE#, ALT_RST#, and STPCLK# low while PCIRST# is
asserted low, and does not drive them high until after PCI reset is released. An anomaly can exist with these
seven signals remaining low during and immediately after PCIRST# is negated. The three instances in which this
can cause a problem are : during a targeted PCI Reset, and in a 82450GX/KX-P6 system, both during power-up
and when BINIT# is asserted on the Pentium Pro processor bus.
Targeted PCI Resets
Systems that support targeted PCI Resets (Resetting the PCI Bus via software control without resetting the
microprocessor) may have a problem with some of the seven signals being asserted low during the targeted
PCI reset. Since the microprocessor can not know when a PCIRST is occurring, this fix must be incorporated in
order to reset the PCI Bus via the register. This will affect all designs using the SIO.A.
The RESET MASK blocking circuit shown above will block signal A from being seen by the CPU during the PCI
Reset. The second flip flop is necessary to avoid a glitch on the Z output to the CPU which can happen if signal
A is asserted simultaneously with PCIRST#.
The blocking circuitry for all of the signals should be incorporated into a PLD. This will ease loading on PCICLK
and PCIRST#. Signals ALT_RST#, IGNNE#, ALT20, STPCLK#, and SMI# should have blocking circuitry.
A
DQ
DQ
RQ
PCICLK
RQ
Z
P C IR S T
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Figure 13. Reset Mask Blocking Logic Using SIO.A
4.10. Utility Bus Peripheral Support
The Utility Bus is a secondary bus buffered from the ISA Bus used to interface with peripheral devices that do
not require a high speed interface. The buffer control for the lower 8 data signals is provided by the SIO/SIO.A
via two control signals; UBUSOE# and UBUSTR. Figure 14 shows a block diagram of the external logic required
as part of the decode and Utility Bus buffer control.
The SIO/SIO.A provides the address decode and three encoded chip selects to support Floppy Controller,
Keyboard Controller, Real Time Clock, IDE Drive, 2 Serial Ports (COM1 and COM2), 1 Parallel Port (LPT1, 2, or
3), BIOS Memory, and Configuration Memory (8 Kbyte I/O Mapped). The SIO/SIO.A also supports Floppy
DSKCHG Function, Port 92 Function (Alternate A20 and Alternate Reset), and Coprocessor Logic (FERR# and
IGNNE# Function)
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