82378ZB Datasheet, PDF (58/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

82378ZB (SIO) AND 82379AB (SIO.A)
E
Bit
Description
3:2 Addressing Mode. The SIO supports both 8 and 16 bit DMA device data sizes. Three data size options
are programmable with bits[3:2]. Both the 8-bit I/O, "count by bytes" mode and the 16-bit I/O, "count by
words" (address shifted) mode are ISA compatible. The 16-bit I/O, "count by bytes" mode is offered as
an extension of the ISA compatible modes. Bits[3:2]=10 is reserved. Byte assembly/disassembly is
performed by the ISA control unit. Each of the data transfer size modes is discussed below.
Bits[3:2]=00: 8-bit I/O, "Count By Bytes" Mode
In 8-bit I/O, "count by bytes" mode, the Current Address Register can be programmed to any address.
The Current Byte/Word Count Register is programmed with the "number of bytes minus 1" to transfer.
Bits[3:2]=01: 16-bit I/O, "Count By Words" (Address Shifted) Mode
In "count by words" mode (address shifted), the Current Address Register can be programmed to any
even address, but must be programmed with the address value shifted right by one bit. The Low Page
and High Page Registers are not shifted during DMA transfers. Thus, the least significant bit of the Low
Page Register is ignored when the address is driven out onto the bus. The Current Byte/Word Count
Register is programmed with the number of words minus 1 to be transferred.
Bits[3:2]=10: Reserved
Bits[3:2]=11: 16-Bit I/O, "Count By Bytes" Mode
In 16-bit "count by bytes" mode, the Current Address Register can be programmed to any byte address.
For most DMA devices, however, it should be programmed only to even addresses. If the address is
programmed to an odd address, the DMA controller does a partial word transfer during the first and last
transfer, if necessary. The bus controller does the Byte/Word assembly necessary to write any size
memory device. In this mode, the Current Address Register is incremented or decremented by two and
the byte count is decremented by the number of bytes transferred during each bus cycle. The Current
Byte/Word Count Register is programmed with the "number of bytes minus 1" to be transferred. This
mode is offered as an extension of the two ISA compatible modes discussed above. This mode should
only be programmed for 16-bit ISA DMA slaves.
1:0 DMA Channel Select. Bits[1:0] select the particular channel that will have its DMA Channel Extend
Mode Register programmed with bits[7:2].
Bits [1:0]
00
01
10
11
Channel
0 (4)
1 (5)
2 (6)
3 (7)
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