82378ZB Datasheet, PDF (47/137 Pages) Intel Corporation – SYSTEM I/O APIC(SIO.A) AND

E
82378ZB (SIO) AND 82379 (SIO.A)
Bit
Description
1:0 Serial Port A Enable: These bits are used to assign serial port A address range (COM1, COM2, or
disable). If either COM1 or COM2 address ranges are selected, the encoded chip select signals
(ECSADDR[2:0]) for Port A will be generated. A PCIRST# sets bits[1:0] to 11 (Port A disabled). Note
that, If Serial Port A and B are programmed for the same I/O address, the encoded chip select signals,
ECSADDR[2:0], for Port B are disabled.
Bit[1:0]
00
01
Function
3F8–3FFh (COM1)
2F8–2FFh (COM2)
Bit[1:0]
10
11
Function
Reserved
Port A disabled
3.1.22. MAR1—MEMCS# ATTRIBUTE REGISTER #1
Address Offset:
Default Value:
Attribute:
54h
00h
Read/Write
RE—Read Enable. When RE=1 (bit 6, 4, 2, 0), the SIO/SIO.A generates MEMCS# for PCI master, DMA, or ISA
master memory read accesses to the corresponding segment. When RE=0, the SIO/SIO.A does not generate
MEMCS# for PCI master memory read accesses to the corresponding segment. When RE=WE=0 (or bit 4=0 in
the MEMCS# Control Register - disabled), the PCI master, DMA, or ISA master can not access the segment.
WE—Write Enable. When WE=1 (bit 7, 5, 3, 1), the SIO/SIO.A generates MEMCS# for PCI master, DMA, or
ISA master memory write accesses to the corresponding segment. When WE=0, the SIO/SIO.A does not
generate MEMCS# for PCI master memory write accesses to the corresponding segment. When the RE=WE
bits=0 (or bit 4=0 in the MEMCS# Control Register - disabled), the PCI master, DMA, or ISA master can not
access the segment.
Bit
Description
Bit
Description
7
0CC000–0CFFFFh Exp. ROM: WE
3
0C4000–0C7FFFh Exp. ROM: WE
6
0CC000–0CFFFFh Exp. ROM: RE
2
0C4000–0C7FFFh Exp. ROM: RE
5
0C8000–0CBFFFh Exp. ROM: WE
1
0C0000–0C3FFFh Exp. ROM: WE
4
0C8000–0CBFFFh Exp. ROM: RE
0
0C0000–0C3FFFh Exp. ROM: RE
3.1.23. MAR2—MEMCS# ATTRIBUTE REGISTER #2
Address Offset:
Default Value:
Attribute:
55h
00h
Read/Write
RE—Read Enable. When RE=1 (bit 6, 4, 2, 0), the SIO/SIO.A generates MEMCS# for PCI master, DMA, or ISA
master memory read accesses to the corresponding segment. When RE=0, the SIO/SIO.A does not generate
MEMCS# for PCI master memory read accesses to the corresponding segment. When RE= WE=0 (or bit 4=0 in
the MEMCS# Control Register - disabled), the PCI master, DMA, or ISA master can not access the segment.
WE—Write Enable. When WE=1 (bit 7, 5, 3, 1), the SIO/SIO.A generates MEMCS# for PCI master, DMA, or
ISA master memory write accesses to the corresponding segment. When WE=0, the SIO/SIO.A does not
generate MEMCS# for PCI master memory write accesses to the corresponding segment. When RE=WE=0 (or
bit 4=0 in the MEMCS# Control Register - disabled), the PCI master, DMA, or ISA master can’t access the
segment.
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