82C836 Datasheet, PDF (98/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s DMA Transfers
DMA Controller
During Demand and Block Transfers, the 82C836 generates multiple sequential transfers.
For most of these transfers only the low-order address bits need to change. The 82C836
updates the middle bits only when necessary. This results in an overall throughput
improvement, since S1 states are not necessary when only the low-order bits are updated.
The DMA Page register file is a set of 16 8-bit registers in the 82C836 used to generate
the high order address bits during DMA cycles. Only eight of the registers are actually
used, but all sixteen are included to maintain IBM PC/AT compatibility. Each DMA
channel has a register associated with it, except for Channel 0 of DMA2, which is used
for internal cascading to DMA1. I/O address assignments for these registers are shown
in Table 8-2.
Table 8-2. DMA Page Register Function I/O Ports
I/O Port
Register
080H
081H
082H
083H
084H
085H
086H
087H
Function
Unused
8-bit DMA Channel 2 (DACK2)
8-bit DMA Channel 3 (DACK3)
8-bit DMA Channel 1 (DACK1)
Unused
Unused
Unused
8-bit DMA Channel 0 (DACK0)
I/O Port
Register
088H
089H
08AH
08BH
08CH
08DH
08EH
08FH
Function
Unused
16-bit DMA Channel 2 (DACK6)
16-bit DMA Channel 3 (DACK7)
16-bit DMA Channel 1 (DACK5)
Unused
Unused
Unused
Refresh cycle
I/O port 80H is normally used externally for diagnotic LEDs, and is updated by the
AT-compatible BIOS during the power-on self-test (POST). The LEDs are optional; they
can either be designed onto the motherboard (usually for evaluation and testing purposes
only), or they can be provided on a removable AT bus add-on card.
Compressed Timing
The DMA subsystem in the 82C836 can be programmed to transfer a word in as few as
three DMA clock cycles (states). The normal AT-compatible DMA cycle consists of
four states: S2, S3, SW, and S4 (this assumes Demand or Block Transfer mode).
Additional DMA wait states (SW) can be programmed. In systems capable of supporting
high throughput, the 82C836 can be programmed to omit the S3 state and assert both
commands in S2. This reduces the minimum cycle to just S2, SW, and S4. If
Compressed Timing is selected, TC is output in S2, and S1 cycles are executed as
necessary to update the middle address bits. Compressed Timing is not allowed in the
memory-to-memory transfer mode.
8-8 Revision 3.0
PRELIMINARY
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