82C836 Datasheet, PDF (45/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s DRAM Interface
System Interface
• Encoded RAS (shared CAS)
This mode is the same as SRA mode, except the four RAS signals are encoded. An
external 74F538 can than be used to decode the four signals into eight RAS lines for
controlling up to eight banks of DRAM (see Figure 5-2). With the advent of 4MB
DRAMs and the 4MB modes in SCATsx, there is probably no further reason to use
encoded RAS in new designs. In addition, the added delay on RAS and CAS signals
(as compared to MRA mode) makes 25MHz zero wait-state operation unachievable if
worst-case DRAM specifications are to be satisfied. Even at reduced speeds, the need
to change the RAS code when switching between memory banks adds a performance
degrading T-state as compared to SRA mode (two T-states as compared to MRA).
Figure 5-2. Encoded RAS Generation
-XMEMR
-REFRESH
From
82C836
-RAS0
-RAS1
-RAS2
74F32
-RAS3
OR-Gate causes all -RAS signals to go low during refresh.
VCC
High except for Refresh.
74F538
12
AL
4
OE1
5
OE2
6
A
7
B
17
C
13
G1
14
G2
15
G3
16
G4
3
Y0
Y1
2
Y2
1
Y3 ¹⁹
Y4 ¹⁸
Y5
8
Y6
9
Y7 ¹¹
-DRAS0
-DRAS1
-DRAS2
-DRAS3
-DRAS4
-DRAS5
-DRAS6
-DRAS7
To DRAMS
ENCODED RAS MODE IS ENABLED BY:
1. ENABLING ICR4EH-7 and
2. SELECTING ONE OF THE RAS ENCODE MODE USING ICR4DH-4:0.
5-4 Revision 3.0
PRELIMINARY
Chips and Technologies, Inc.