82C836 Datasheet, PDF (105/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

DMA Controller
DMA Register Descriptions s
Status Register
The status of all four channels can be determined by reading the Status Register.
Information is available to determine if a channel has reached terminal count and whether
an external service request is pending. Bit 0-3 of this register are cleared by a RESET, a
Master Clear, or each time a Status Read takes place. Bits 4-7 are cleared by a RESET, a
Master Clear, or the pending request bits. The channel number corresponds to the bit
position. Refer to Figure 8-8.
Figure 8-8. Status Register (Read Only)
B7 B6 B5 B4 B3 B2 B1 B0
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TC<3:0> Terminal Count
DRQ<3:0> DMA Request
bits: B0-B3 TC<3:0> Terminal count reached.
B4-B7 DRQ<3:0> DMA request pending
Temporary Register
The Temporary Register (not accessible in AT-compatible architectures, including
SCATsx) is used as a temporary holding register for data during memory-to-memory
transfers. The register is loaded during the first cycle of a memory-to-memory transfer
from XD0-7. During the second cycle of the transfer, the 8237-compatible subsection
attempts to output the data on the XD0-7 pins, but there is no bus steering logic
implementing this data path. Data from the last memory-to-memory transfer remains in
the register unless a RESET or a Master Clear occurs.
Chips and Technologies, Inc.
PRELIMINARY
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