82C836 Datasheet, PDF (156/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s CPU Access to AT-Bus
System Timing Relationships
If -RAS was active before HLDA was asserted, -RAS is forced high immediately (rising
edge of HLDA). Additional memory timing during DMA and Master cycles is shown in
Figure 11-15.
To meet CPU timing requirements, HOLD is synchronized to PROCCLK. From the
middle of the final S4 state to the falling edge of HOLD there is a minimum delay of two
complete cycles of the 14.3MHz OSC clock and an additional minimum delay of one
complete cycle of PROCCLK. The involvement of the 14.3MHz clock is for arbitration
with refresh.
S0 is entered after assertion of HOLD, S0 is then repeated as needed until HLDA is
detected. When HLDA is detected high at mid-S0, S1 will be entered either immediately
(DMA Channels 5-7) or after three more S0 states (Channels 0-3). The additional S0
states for Channels 0-3 occur because of the cascading between those channels and
Channels 5-7.
If the DMA clock is set to BUSCLK rather than BUSCLK/2, each S state is still one
cycle of the DMA clock, and, except for the frequency of the DMA clock, S-state timing
remains the same as described previously.
DRQ/DACK Scanning in MRA Mode
Figure 11-14 shows how DRQ scanning and DACK encoding are performed in Multiple
RAS Active (MRA) mode. The seven DRQ signals are continuously scanned, two at a
time, and latched inside the 82C836. One pair of DRQ signals is scanned every 70ns
(based on the 14.3MHz clock source) using an external 74F153 multiplexer. If the
82C836 internal 8237A-compatible logic decides to recognize one of the internally
latched DRQ signals, scanning stops and locks onto the corresponding DRQ signal. At
about the same time, the DACK signal issued by the internal 8237A-compatible logic is
encoded and generated on the DACKA-C lines. Finally, -DACKEN goes active (low),
enabling the external 74ALS138 decoder to reconstruct the appropriate DACK output.
The scanning mechanism remains frozen on the selected DRQ signal until the DMA
transfer is completed and the corresponding DACK signal is deasserted. Usually this will
occur in response to external logic deasserting the DRQ signal. Scanning then resumes
from the lock-in point and continues until the next DRQ signal is recognized by the
internal 8237A-compatible logic.
It is possible for more than one DRQ signal to have been scanned and latched inside the
82C836 before the internal 8237A-compatible logic decides to recognize one of the
internally latched DRQs. In fact, if a DMA channel has not been enabled by software, a
latched DRQ for the disabled DMA channel will never be recognized by the
8237A-compatible until software enables the channel logic. Meanwhile, other DMA
channels are free to function normally as programmed by the software.
Figure 11-14 illustrates the DRQ scanning process followed by recognition of DRQ0
or DRQ5.
Only four cycles of the 14.3 MHz clock are needed to completely scan and internally
latch all seven DRQ signals.
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