82C836 Datasheet, PDF (178/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s AC Characteristics 16- and 20MHz
System Characteristics
Table 12-16. DMA and AT-Bus Master Access to Local Memory----Formula Specifications
Symbol
te230
te233
te235
te239
te240
te242
Critical Path
RAS precharge before refresh
MWE rise before CAS fall (read)
RAS precharge, Master
Master read, access from RAS
Row address to RAS
Master write, SDIR fall
Formula
t230-t263-t265
t233-t102
t235-t239
t239+t145
t240-t239+t106
t242+t147
16MHz
Min. Max.
---- 27
---- 35
---- 16
---- 51
---- 25
---- 65
20MHz
Min. Max.
---- 27
---- 24
---- 16
---- 51
---- 25
---- 65
Table 12-17. DMA and AT-Bus Master Access to Local Memory----Input Requirements
Symbol
t250
t251
Parameters
PARL, PARH setup before -XMEMR rise
during mem read
PARL, PARH hold after -XMEMR rise
during mem read
16MHz
Min. Max.
20 ----
0
----
20MHz
Min. Max.
20 ----
0
----
Refresh
The refresh timing specifications and requirements are shown in Tables 12-18 through
12-20.
Table 12-18. Refresh----Output Responses
Symbol
t260
t261
t262
t263
t264
t265
t266
t267
t268
Parameters
-REFRESH active from HLDA
-REFRESH float from OSC2 rise
Refresh address valid from -REFRESH active ^†
-XMEMR active from OSC2 rise
-XMEMR inactive from OSC2 rise
-RAS0, -RAS3 active from -XMEMR fall
-RAS0, -RAS3 inactive from -XMEMR rise
-RAS1, -RAS2 active from -XMEMR fall
-RAS1, -RAS2 inactive from -XMEMR rise
† Refresh address refers to MODA0, A0-9, and MA0-9.
** 40ns maximum for 836A.
16MHz
Min. Max.
---- 71
---- 55
---- 45**
---- 60
---- 55
---- 35
---- 30
---- 75
---- 75
20MHz
Min. Max.
---- 71
---- 55
---- 45**
---- 55
---- 50
---- 30
---- 25
---- 70
---- 70
1 2-1 0 Revision 3.0
PRELIMINARY
Chips and Technologies, Inc.