82C836 Datasheet, PDF (42/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

Section 5
System Interface
ROM/Shadow RAM Interface
Memory accesses in the range 0C0000H-0FFFFFH can be programmed via internal
configuration registers 48H through 4CH to map to ROM, local RAM, or external RAM,
as follows:
• ROM can be enabled or disabled in eight independent blocks of 32KB in the range
0C0000H-0FFFFFH.
• Local RAM can be enabled or disabled in 24 independent blocks of 16KB throughout
the range 0A0000H-0FFFFFH.
• Local RAM the range 0C0000H-0FFFFFH can be write protected in eight
independent blocks of 32 KB.
• If neither ROM nor RAM is enabled in a particular address block, memory accesses
to that block go to the AT bus.
Memory accesses in the range FC0000H-FFFFFFH are treated as follows:
• The default is for all memory accesses in this range go to ROM in the range of
0C0000H-0FFFFFH, regardless of whether or not shadow RAM has been enabled
in the target area.
• There is a programmable option to reduce the size of this special area to the top
128KB (FE0000H-FFFFFFH) instead of the top 256KB (see ICR 4E bit 4).
• There is another programmable option to map the affected high memory area (starting
at FC0000H or FE0000H) to shadow RAM instead of ROM (see ICR 46H bit 5). This
option is intended for laptop architectures in which the initial CPU code fetches
following CPU reset need to map into shadow RAM instead of ROM.
The 82C836 provides one ROM chip select (-ROMCS), which is active for all ROM
accesses.
On-board ROM can be either 8-bit wide or 16-bit wide and must be connected to the
XD-bus. To select 16-wide width, the DACK7 line must be pulled low with a 4.7K ohm
resistor; to select 8-bit mode, the line must be pulled high with a 4.7K ohm resistor. The
82C836 asserts -MEMCS16 during all ROM cycles if 16-bit mode is selected.
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