82C836 Datasheet, PDF (101/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

DMA Controller
DMA Register Descriptions s
reading the Mode register location. A clear Mode Register Counter command is
provided to allow the CPU to restart the mode read process at a known point. During
mode read operation, bits 0 and 1 are one. Refer to Figure 8-3.
Figure 8-3. Mode Register
B7 B6 B5 B4 B3 B2 B1 B0
_________________ ________ ________ _________________ _________________
CS<1:0> Channel Select
TT<1:0> Type of Transfer
AI
Auto-Initialization
DEC Address Counter Direction
M<1:0> Mode Selection
bits: B0-B1
B2-B3
B4
B5
B6-B7
CS<1:0>
TT<1:0>
AI
DEC
M<1:0>
Channel Select bits 1 and 0 determine the channel for which the
Mode register is written. Read back of a Mode register results in bits
1 and 0 both being ones. Channel Select is as follows:
• Channel 0 Select
• Channel 1 Select
• Channel 2 Select
• Channel 3 Select
when CS1 = 0 and CS0 = 0
when CS1 = 0 and CS0 = 1
when CS1 = 1 and CS0 = 0
when CS1 = 1 and CS0 = 1
Bits 2 and 3 control the type of transfer that is to be performed. The
type of transfer is as follows:
• Verify Transfer
• Write Transfer
• Read Transfer
• Illegal
when TT1 = 0 and TT0 = 0
when TT1 = 0 and TT0 = 1
when TT1 = 1 and TT0 = 0
when TT1 = 1 and TT0 = 1
The Auto-Initialization function is enabled by writing a one in bit 4
of the Mode register.
Determines direction of the address counter. A one in bit 5
decrements the address after each transfer.
Mode selection for each channel is accomplished by bit 6 and 7. The
type of modes are as follows:
• Demand Mode
• Single Cycle Mode
• Block Mode
• Cascade Mode
when M1 = 0 and M0 = 0
when M1 = 0 and M0 = 1
when M1 = 1 and M0 = 0
when M1 = 1 and M0 = 1
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