82C836 Datasheet, PDF (133/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

Section 11
System Timing Relationships
This section contains timing diagrams for all the major timing sequences in an
AT-compatible SCATsx system. The diagrams emphasize the functional timing
relationships between signals (i.e., what conditions cause the various timing events).
For clarity, propagation delays and rise/fall times are either not shown or not drawn
to scale.
Each diagram is accompanied by explanatory notes describing important aspects of the
timing sequence.
CPU Access to AT-Bus
Figure 11-1 shows a bus convert read or write. -CMD refers to the following possibilities:
• -XMEMR for a memory read cycle
• -XMEMW for a memory write cycle
• -XIOR for an I/O read cycle
• -XIOW for an I/O write cycle
-LOMEGCS is generated during memory cycles in which the memory address is in the
first 1MB of address space i.e., 0-0FFFFFH. The only intended use of -LOMEGCS
outside the 82C836 is to enable the -SMEMR and -SMEMW drivers, allowing -SMEMR
to be asserted if -XMEMR is asserted, or -SMEMW if -XMEMW is assererted.
If the cycle is a memory read in an address range allocated for on-board ROM, -ROMCS
is asserted at the same time as -XMEMR ( ‘‘same time’’ here means on the same clock
edges, neglecting propagation delays).
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