82C836 Datasheet, PDF (114/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s Configuration Registers
82C386 CHIPSet Data Sheet
Table 10-2. Index 40H----82C836 Version, Read Only
Bit
Name
Description
7-4
Family Type
Identifies specific part in pin-compatible family. SCATsx denoted by 0001.
3-0
Device Revision Identifies revision level of the 82C836 silicon, starting with 0000. The
Code
82C836B has revision code 0100; the 82C836A has code 0011.
Table 10-3. Index 41H----Channel Environment
Bit
Name
7
Fast Refresh
Description
This bit controls an improvement in HOLD timing to reduce total HLDA
time during refresh. Up to 1% performance improvement possible.
0 = Enable fast refresh (default)
1 = Disable; follow revision 1 refresh timing
This bit is intended to remain zero except for test purposes.
6
Early READY
Allows external devices to assert READY during the first T2 after T1 to
Enable
terminate the memory cycle after only two T-states. Enables ‘‘Early Wait
State’’ for local memory read not ‘‘claimed ’’ by early READY.
1 = Enable*
0 = Disable (default)
5
LBA Enable
Allows external devices to assert LBA (0WS pin) during the first T2 after T1
to prevent the 82C836 from starting a memory cycle. Enables Early Wait
State for local memory read not claimed by LBA.
1 = Enable*
0 = Disable (default)
If both Early READY and LBA are enabled, there will still be only one early
wait state for unclaimed local memory reads.
4
Bus Convert
Enable conversion of 8-bit AT bus reads into 16-bit reads so that a local
Enable
cache, if present, can cache 16 bits at a time.
1 = Enable
0 = Disable (default)
This feature does not apply to 8-bit AT bus memory resources residing in
the first 1MB. Also, the usual AT-compatible conversion of ‘‘even word’’
accesses into paired byte operations is not affected by this bit. This bit has
no effect unless bit 6 is set.
3-2
BUSCLK SEL
Selects AT bus clock.
00 = Selects BUSCLK as CXIN/4
01 = Selects BUSCLK as CXIN/5 (default)
10 = Selects BUSCLK as CXIN/6
11 = (Reserved)
1-0
Refresh
Width
These bits specify -XMEMR pulse width during a refresh cycle. These pulse
widths are derived from OSC. The width of -XMEMR directly affects the
overall bus cycle time for refresh operations.
00 = 104ns
01 = 210ns
10 = 280ns (default)
11 = 350ns
* Bits 5 and 6 must remain zero if CPU pipeline mode is enabled.
1 0-2 Revision 3.0
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