82C836 Datasheet, PDF (50/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

System Interface
DRAM Interface s
If any two bank pairs are of the same size, but the other pair is empty or has only one
bank populated, then two-way page interleaving is automatically performed in the two
same-size banks. The banks are paired as follows: 0 and 1, 2 and 3, 4 and 5, 6 and 7. In
addition, Banks 1 and 2 are two-way page interleaved in configurations 09H and 0AH,
with noninterleaved page mode in the remaining banks. Thus, the only configurations in
which no interleaving occurs are 00H, 01H, 08H, 0BH, and 18H.
A RAS timeout feature is provided to support DRAMs requiring a 10 microsecond
maximum RAS-active time. If the timeout is enabled, RAS is not allowed to remain low
continuously for more than about 9.5 microsecond. If the timeout is disabled, periodic
refresh cycles limit the maximum possible RAS active time to about 15 microseconds.
SCATsx Memory Address Mapping Modes
The following table summarizes how CPU address bits are mapped into DRAM row
and column address bits and which bits determine bank selection. The ‘‘R’’ bits do not
necessarily map in an exact one-to-one bit order, but the R bits as a group do correspond
to the CPU address bits indicated. ‘‘Page Size’’ refers to the block size accessible by
changing column address bits only.
Table 5-4. Memory Address Mapping Modes
CPU Address
Bit
4MW, 2-way
4MW, Page only
1MW, 4-way
1MW, 2-way
1MW, Page only
256KW, 4-way
256KW, 2-way
256KW,
Page Only
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R R R R R R R R * C C C C C C C C C C C ----
---- R R R R R R R R R R R C C C C C C C C C C C ----
---- R R R R R R R R R R * * C C C C C C C C C C ----
---- ---- R R R R R R R R R R * C C C C C C C C C C ----
---- ---- ---- R R R R R R R R R R C C C C C C C C C C ----
---- ---- ---- R R R R R R R R R * * C C C C C C C C C ----
---- ---- ---- ---- R R R R R R R R R * C C C C C C C C C ----
---- ---- ---- ---- ---- R R R R R R R R R C C C C C C C C C ----
Page
Size
4KB
4KB
2KB
2KB
2KB
1KB
1KB
1KB
R = Row address bit
C = Column address bit
* = Bank select bit for interleaving
---- = High level decoding and byte Selection
W = Word (even and odd bytes)
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