82C836 Datasheet, PDF (58/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

System Interface
Figure 5-4. -READYO Interface
-READYO
(From 80387sx)
Numeric Coprocessor Interface s
74F125
-READY
(To 80386sx)
74F125
74F125
74F125
TIME DELAY
(For delayed -READY TURNOFF on rising edge of -READYO)
Additional considerations are as follows:
• Whenever a coprocessor error has occurred and the coprocessor is not busy, external
logic should force PEREQ to the 80386sx active (high) to allow the 80386sx to finish
any remaining I/O cycles in the current (error causing) coprocessor instruction. This
mode, forcing PEREQ when the coprocessor is not busy, should end as soon as the
80386sx acknowledges the coprocessor error condition, as indicated by the 82C836
-BUSY output going inactive. A circuit for accomplishing this is shown in the system
schematics. Due to pin limitations, it was not possible to incorporate this logic inside
the 82C836.
• Certain software packages are known to rely on reading coprocessor status to
determine coprocessor presence or absence. To guarantee that coprocessor status will
be invalid in the event that no coprocessor is preset, a low-order data bit, such as D0,
should be pulled down instead of pulled up (see Appendix A, System Schematics).
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