82C836 Datasheet, PDF (166/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s CPU Access to AT-Bus
System Timing Relationships
The various time delays during standby refresh are generated via asynchronous
gate delays.
Standby refresh is based on the 32KHz time base. The 32KHz clock should be designed
to operate on battery power (along with the 82C836) when main power has been turned
off. Each edge of the 32KHz clock triggers a CAS-before-RAS refresh cycle. The
DRAMs, of course, must also operate on battery power in order to preserve their contents
during main power interruptions. There should be either no buffering of -RAS, -CAS,
and -MWE to the DRAMs, or battery backed buffers should be used.
As shown in Figure 11-18, the transition from normal refresh to standby refresh occurs
automatically in response to PWRGOOD going low. The transition back to normal
refresh after PWRGOOD goes back high is somewhat more complicated. First, BIOS
must restart normal refresh by appropriately programming the 14.3MHz based refresh
timer. After the refresh timer starts running again, 32KHz based refresh is stopped and
14.3MHz based refresh starts up.
For laptop applications, both normal refresh and standby refresh should use
CAS-before-RAS protocol in which the DRAMs generate their own refresh addresses
internally.
Power Turn-On and System Reset
Figure 11-19 shows what happens immediately following power turn-on. Except for
VCC and PS, this sequence applies to the cycling of PWRGOOD by means of a hardware
reset switch as well as power turn-on.
Figure 11-19. Power-On
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PRELIMINARY
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