82C836 Datasheet, PDF (184/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s AC Characteristics 25MHz
System Characteristics
Table 12-30. CPU to Local Memory----Input Requirements
Symbol
t120
t121
t122
t123
Parameters
PARL, PARH setup before PROCCLK rise during read
PARL, PARH hold after PROCCLK rise during read
D0-15 setup before PROCCLK rise during read
D0-15 hold after PROCCLK rise during read
Min.
Max.
7
----
5
----
7
----
5
----
CPU to AT-Bus, On-Board I/O, and ROM
Tables 12-31 through 12-33 shows the CPU AT bus, on-board I/O, and ROM accesses.
Table 12-31. CPU to AT-Bus, On-Board I/O, and ROM----Output Responses
Symbol
t130
t131
t132
t133
t134
t135
t136
t137
t138
t139
t140
t141
t142
t143
t144
t145
t146
t147
t148
Parameters
LOMEGCS delay from PROCCLK rise
-NA delay from PROCCLK rise (C _L = 25pF)
-READY delay from PROCCLK rise
ALE rise from BUSCLK low
ALE fall from BUSCLK high
Command and -ROMCS active from BUSCLK
Command and -ROMCS inactive from BUSCLK rise
MODA0 delay from PROCCLK rise
MODA0 rise from BUSCLK fall during bus convert
MODA20 delay from A20 (if MODA20 enabled)
MODA20 delay from HOLD fall
SDIRL, H delay from PROCCLK rise
XD0-15 delay from PROCCLK rise during write
XD0-15 turn-on delay from PROCCLK rise
XD0-15 turn-off delay from PROCCLK rise
XD0-15 delay from D0-15 during CPU write or Master read
XD0-7 delay from D8-15 during CPU write
(byte swap)
D0-15 delay from XD0-15 during CPU read or DMA/Master write
D8-15 delay from XD0-7 during CPU read (byte swap) or DMA
Min.
Max.
----
35
----
15
4
31
----
25
----
15
----
30
----
25
----
30
----
20
----
35
----
40
----
50
----
50
5
----
----
50
----
30
----
70
----
25
----
40
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