82C836 Datasheet, PDF (75/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s Counter Operation
Real Time Clock and Internal Timer Registers
process is repeated. In Mode 2, the counter continues counting (if GATE2 = 1) and
generates an OUT2 pulse every n TMRCLK cycles. Note that a count of one is illegal
in Mode 2.
GATE2 = 0 disables counting and immediately forces OUT2 high. A trigger releads
the CE on the TMRCLK pulse. Thus GATE2 can be used to synchronize the counter
to external events.
Writing a new count while counting does not affect current operation unless a trigger
is received. Otherwise, the new count is loaded at the end of the current counting
cycle.
• Mode 3----Square Wave Generator
Mode 3 is similar to Mode 2 in every respect except for the duty cycle of OUT2.
OUT2 is set high initially, and remains high for the first half of the count. When the
first half of the initial count expires, OUT2 goes low for the remainder of the count. If
the counter is loaded with an even count, the duty cycle of OUT2 is 50% (high = low
= n/2). For odd count values, OUT2 is high one TMRCLK cycle longer than it is low.
Therefore, high = (n + 1)/2 and low = (n - 1)/2.
• Mode 4----Software Triggered Strobe
Writing the Control Word causes OUT2 to go initially. Expiration of the initial count
causes OUT2 to go low for one TMRCLK cycle. GATE2 = 0 disables counting but
has no effect on OUT2. Also, a trigger does not reload the CE.
The counting sequence is started by writing the initial count. The CE is loaded on the
TMRCLK pulse after initialization. The CE begins decrementing one TMRCLK
pulse later. OUT2 goes low for one TMRCLK cycle, (n + 1) cycles after the initial
count is written. If a new initial count is written during a counting sequence, it is
loaded into the CE on the next TMRCLK pulse and the sequence continues from the
new count. This allows the sequence to be retriggered by software.
• Mode 5----Hardware Triggered Strobe
Writing the Control Word causes OUT2 to go high initially. Counting is started by a
trigger. The expiration of the initial count causes OUT2 to go low for one TMRCLK
cycle. GATE2 = 0 disables counting.
The CE is loaded during counting, the current counting sequence is not affected unless a
trigger occurs. A trigger causes the counter to be reloaded from CIL and CIH making the
counter re-triggerable.
6-1 6 Revision 3.0
PRELIMINARY
Chips and Technologies, Inc.