82C836 Datasheet, PDF (79/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

Interrupt Controller
Controller Operation s
Controller Operation
Figure 7-2 shows a block diagram of the major elements in the interrupt controller. The
Interrupt Request Register (IRR) is used to store requests from all the channels requesting
service. Interrupt Request Register bits are labeled using the channel name IR<0:7>.
The In-Service Register (ISR) contains all the channels currently being serviced (more
than one channel can be in service at the same time). In-Service Register bits are labeled
IS<0:7>. The Interrupt Mask Register (IMR) allows the CPU to disable any or all of the
interrupt channels. The Priority Resolver evaluates inputs from the above three registers,
issues an interrupt request, and latches the corresponding bit into the In-Service Register.
During interrupt acknowledge cycles, a master controller outputs a code to the slave
device that is compared in the Cascade Buffer/Comparator with a three bit ID code
previously written. If a match occurs in the slave controller, it generates an interrupt
vector. The contents of the Vector Register are used to provide the CPU with an
interrupt vector during Interrupt Acknowledge (INTA) cycles.
Figure 7-2. Interrupt Controller Block Diagram
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PRELIMINARY
Revision 3.0 7-3