82C836 Datasheet, PDF (154/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s CPU Access to AT-Bus
System Timing Relationships
DMA Channels 0-3 are designed for 8-bit transfers involving 8-bit I/O resources. The
memory resources can be either 8-bit or 16-bit. -IOCS16 is ignored, but -MEMCS16 is
used in conjunction with SA0 and -SBHE to control byte swapping between SD0-7 and
SD8-15. Address bits 0-15 increment or decrement by one after each DMA cycle.
Software intervention is needed to change the contents of address bits 16-23.
DMA Channels 5-7 are designed for 16-bit transfers involving 16-bit I/O resources. The
memory resources must be 16-bit, also. -IOCS16 and -MEMCS16 are ignored, and
-BHE and A0 are both driven low. Address bits 1-16 increment or decrement by one
(i.e., address 0-16 increments or decrements by two, always even) after each DMA cycle.
Software intervention is needed to change the contents of address bits 17-23.
DMA timing is driven by the internal DMA clock, which is either the same as BUSCLK
or reduced to BUSCLK/2 (programmable). Figure 11-12, shown earlier, identifies
hardware defaulting timing which is AT-compatible.
• The default DMA clock is BUSCLK/2. Timing is divided into S states, each
consisting of one DMA clock.
• The middle address bits (8-15 or 9-16) are updated at the middle of S1. Low-order
address bits (0-7 or 1-8) are incremented at the middle of each S2.
• -XIOR is asserted (if needed) at mid-S2, but -XMEMR is asserted (if needed) at
mid-S3. Assertion of -XMEMR can be changed to mid-S2 using ICR 01H.
• -XIOW and -XMEMW are asserted as needed at mid-S3. This can be changed to
mid-S2 using extended write mode.
• There is one DMA wait state. SW (programmable up to four), and all commands are
de-asserted at mid-S4.
Using compressed mode, the S3 states can be eliminated. S3 events, in that case, occur
in S2 instead of S3. SW states are not affected.
TC, if asserted, coincides with -XMEMW or -XIOR.
Detection of IOCHRDY low at the end of SW causes additional SW states to be inserted
until IOCHRDY is detected high at the end of an added SW. Although IOCHRDY
during DMA is normally controlled only by memory resources, not I/O resources, the
82C836 has no means to distinguish the source of an IOCHRDY de-assertion and will
respond in the same way regardless of which resource is controlling IOCHRDY.
DREQ is also sensed at the end of each SW. If DREQ is detected low, the DMA
operation terminates after the end of the current DMA cycle. DMA and master access to
local memory is shown in Figure 11-13.
1 1 -22 Revision 3.0
PRELIMINARY
Chips and Technologies, Inc.