82C836 Datasheet, PDF (115/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

82C386 CHIPSet Data Sheet
Configuration Registers s
Index 42H and Index 43H are reserved.
Index 44H controls whether peripherals are accessed on the XD-bus or SD-bus. The
SDIRH and SDIRL SD-bus controls are affected by bits in this register.
Table 10-4. Index 44H----Peripheral Control
Bit
Name
7
----
6
Video on the
XD-bus
Description
Reserved.
This bit indicates whether or not a video controller is resident on the XD-bus.
0 = Video controller is on the SD-bus.
1 = Video controller is on the XD-bus.
The I/O address ranges covered for the video controller are 0102H-0104H,
03B0H-03DFH, and 46E8H. Video memory address range is 0A0000H
through 0BFFFFH. The power-on default value of this bit is determined by
the state of -DACK2 (inverted) during power-on reset. -DACK2 high causes
this bit to default to zero. If the -DACK2 strap option is used to denote
something other than ‘‘Video on X-Bus,, ’’ software (BIOS) must write this
ICR bit to the correct value before accessing the video controller.
5
Game Port on
This bit specifies whether or not the game port is resident of the XD-bus.
the XD-bus
The I/O address range covered 0200H-0207H.
0 = Game port on the SD-bus (default)
1 = Game port on the XD-bus.
4
Serial Port
Specifies whether or not serial port 2 is resident on the XD-bus. The I/O
Channel 2 on
address range is 02F8H-02FFH.
the XD-bus
0 = Serial port 2 on the SD-bus (default).
1 = Serial port 2 on the XD-bus.
3
Serial Port
Specifies whether or not serial Port 1 is resident on the XD-bus. The I/O
Channel 1 on
address range is 03F8H-03FFH.
the XD-bus
0 = Serial port 1 on the SDS-bus (default)
1 = Serial Port 1 on the XD-bus.
2
Parallel Port on
Specifies whether or not a parallel port is resident on the XD-bus. The
the XD-bus
address range covered 0378H-037FH.
0 = Parallel port on the SD-bus (default)
1 = Parallel port on the XD-bus.
1
HDC/FDC on
Specifies whether or not the hard drive and diskette drive controllers are
the XD-bus
resident on the XD-bus. The I/O address ranges covered are 01F0H-01F7H
and 03F0H-03F7H, as well as DMA Channel 2 (-DACK2)
0 = HDC/FDC on the SD-bus (default).
1 = HDC/FDC on the XD-bus.
0
Coprocessor
Determines whether READY is controlled by the 82C836 or 80387sx during
Ready
coprocessor accesses. If no coprocessor is present, the 82C836 always
controls READY during coprocessor I/O cycles, regardless of the state of
this bit. If a coprocessor is present and the READYO logic is not
implemented, BIOS should set this bit to one. Otherwise, the system will
hang due to lack of READY as soon as POST or other software tries to
access the coprocessor.
0 = 80387sx generates READY (default)
1 = 82C836 generates READY
Note: Memory resources on the XD bus can be ROM or video RAM. The only DMA device allowed on the X D bus is
the HDC/FDC. The BIOSes associated with video and/or HDC should be included in the -ROMCS decoding (ICR 48H); they
are not included in SDIR decoding (ICR 44H) for XD-bus peripherals. 10K pull-up resistors should be used on XD0-15 in
systems that use XD-bus peripherals so read cycles from unused XD-bus addresses will receive 0FFH da ta.
Chips and Technologies, Inc.
PRELIMINARY
Revision 3.0 1 0-3