82C836 Datasheet, PDF (78/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s Interrupt Controller
Interrupt Controller
The two devices are interconnected and must be programmed to operate in Cascade
Mode (see Figure 7-1) for proper operation of all 16 interrupt channels. INTC1 is located
at addresses 020H-021H and is configured for Master operation in Cascade Mode.
INTC2 is a slave device and is located at 0A0H-0A1H. The Interrupt Request output
signal from INTC2 (INT) is internally connected to the interrupt request input Channel 2
(IR2) of INTC1. The address decoding and Cascade interconnection matches that of the
IBM PC/AT.
Figure 7-1. Cascaded Interrupt Controllers
Two additional interconnections are made to the interrupt request inputs of the interrupt
controllers. The output of Timer 0 in the Counter/Timer subsystem is connected to
Channel 0 (IR0) of INTC1. An Interrupt request from the Real Time Clock is connected
to Channel 0 (IR0) of INTC2.
The following description of the Interrupt Subsystem pertains to both INTC1 and INTC2
unless otherwise noted. Whenever register addresses are used, the address for the INTC1
register is listed first, and the address for the INTC2 register follows in parentheses, e.g.,
020H (0A0H).
7-2 Revision 3.0
PRELIMINARY
Chips and Technologies, Inc.