82C836 Datasheet, PDF (120/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s Configuration Registers
82C386 CHIPSet Data Sheet
Index Register 4BH controls whether shadow RAM is enabled or disabled in the 16KB
address ranges specified as follows:
1 = Enable RAM
0 = Disable RAM
Default for all bits is 0.
Table 10-10. Index 4BH----Shadow RAM Enable 2
Bit
Description
7
0DC000H-0DFFFFH RAM Enable
6
0D8000H-0DBFFFH RAM Enable
5
0D4000H-0D7FFFH RAM Enable
4
0D0000H-0D3FFFH RAM Enable
3
0CC000H-0CFFFFH RAM Enable
2
0C8000H-0CBFFFH RAM Enable
1
0C4000H-0C7FFFH RAM Enable
0
0C0000H-0C3FFFH RAM Enable
Index Register 4CH controls whether shadow RAM is enabled or disabled in the 16KB
address ranges specified as follows:
1 = Enable RAM
0 = Disable RAM
The default for all bits is 0.
Table 10-11. Index 4CH----Shadow RAM Enable 3
Bit
Description
7
0FC000H-0FFFFFH RAM Enable
6
0F8000H-0FBFFFH RAM Enable
5
0F4000H-0F7FFFH RAM Enable
4
0F0000H-0F3FFFH RAM Enable
3
0EC000H-0EFFFFH RAM Enable
2
0E8000H-0EBFFFH RAM Enable
1
0E4000H-0E7FFFH RAM Enable
0
0E0000H-0E3FFFH RAM Enable
Note: Do not enable ROM and shadow RAM in the same address range at the same time; do not enable sh
when using memory configuration #03H (640K + 384K).
adow RAM
1 0-8 Revision 3.0
PRELIMINARY
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