82C836 Datasheet, PDF (97/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

DMA Controller
DMA Transfers s
originally written by the CPU, are reloaded into the Current Address and Current Word
Count registers (both the base and current registers are loaded during a CPU write cycle).
The base register remains unchanged during DMA active cycles and can only be changed
by the CPU. If the channel is programmed to auto-initialize, the request mask bit is not
set upon reaching terminal count. This allows the DMA to continue operation without
CPU intervention.
During memory-to-memory transfers, the Word Count registers of both Channel 0 and
Channel 1 must be programmed with the same starting value for full auto-initialization.
If Channel 0 reaches terminal count before Channel 1, then Channel 0 and Channel 1
must be programmed with the same starting value for full auto-initialization. If Channel
0 reaches terminal count before Channel 1, then Channel 0 reloads the starting address
and word count, and continues transferring data from the beginning of the source block.
Should Channel 1 reach terminal count first, it reloads the current registers and Channel 0
remains uninitialized.
DREQ Priority
The 82C836 supports two schemes for establishing DREQ priority. The first is fixed
priority, which assigns priority based on channel position. In this method, Channel 0 is
assigned the highest priority. Priority assignment then progresses in order down through
channels, with Channel 3 receiving the lowest priority.
The second type of priority assignment is rotating priority. In this scheme the ordering of
priority from Channel 0 to Channel 3 is maintained but the actual assignment of priority
changes. The channel most recently serviced is assigned the lowest priority and, since
the order of priority assignment remains fixed, the remaining three channels rotate
accordingly.
In instances where multiple requests occur at the same time, the 82C836 issues an HRQ
but does not freeze the priority logic until HLDA is returned. Once HLDA becomes
active, the priority logic is frozen and DACK is asserted on the highest requesting
channel. Priority is not re-evaluated until HLDA is deactivated.
Address Generation
DMA addresses consist of three separate parts:
• The low-order bits (0-7 or 1-8) are automatically incremented after each DMA
transfer (during state S1 or S2).
• The middle bits (8-15 or 9-16) are updated only when there is a carry from the low
order bits. An S1 state is required whenever the middle bits need to be updated.
• The high-order bits (16-23 or 17-23) come from the DMA Page registers, separate
from the 8237-compatible DMA subsections. The high-order bits cannot be updated
without software intervention.
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