82C836 Datasheet, PDF (128/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s Configuration Registers
82C386 CHIPSet Data Sheet
The only known case where Index Register 64H bit 7 makes any difference in system
operation is when running certain diagnostic programs that use CPURST on a system
having an 82C835 cache controller, but with cache operation disabled (CPU reset without
XRST is often used to return the CPU to real mode from protected mode). The 82C835
needs to see READY in response to every ADS, including ADS pulses occuring during
CPU reset. Setting this bit to one allows the 82C836B to finish every CPU cycle started
during CPU reset, including assertion of READY. This bit might need to be zero if
software attempts to perform a cache read miss (cache enabled) or memory write
operation during CPU reset. Normally, however, software will halt the CPU or execute a
‘‘jump to self ’’ loop (cache read hits) while waiting for CPU reset to take effect. Thus, it
should be safe always to set bit 7 to one.
EMS Page Registers
This section lists the bit assignments for the three I/O ports used to access the four EMS
page registers.
I/O port 208H (or 218H) accesses bits 21 through 14 of the address of the 16KB target
page to be mapped into the corresponding page window in the 64KB remappable address
range. The page register accessed by this port is selected by port 20AH (or 21AH).
Table 10-20. Port 208H----Target Page Address
Bit
Description
Bit
7
A21 of target page address
3
6
A20 of target page address
2
5
A19 of target page address
1
4
A18 of target page address
0
Description
A17 of target page address
A16 of target page address
A15 of target page address
A14 of target page address
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