82C836 Datasheet, PDF (121/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

82C386 CHIPSet Data Sheet
Configuration Registers s
Table 10-12. Index 4DH----DRAM Configuration
Bit
Description
7
CAS
Wait State
6
RAS Timeout
5
CAS Wait State
for Read
4-0
CFG4-0
Allows an additional T-state (two PROCCLK cycles) to be inserted on all
local memory accesses. The added T-state is inserted during the CAS
active interval, extending the width of the CAS pulse.
0 = no added Wait State (default)
1 = Wait State enabled
Disables the RAS Timeout feature.
0 = RAS timeout enable (default)
1 = RAS timeout disabled
Allows the CAS Wait State (bit 7 above) to be inserted on local memory
reads, but not on writes.
0 = Wait State controlled by bit 7 above (default)
1 = CAS Extend Wait State Enabled on memory read, regardless of
bit 7; wait state for write still controlled by bit 7.
These bits specify the DRAM configuration as described in Section 5,
System Interface, subsection titled DRAM Interface. The default value
after reset is 00001 (512KB total DRAM).
Table 10-13. Index 4EH----Extended Memory Boundary
Bit
Name
Description
7
RAS Encode Enable This bit changes the four -RAS lines into three encoded -RAS lines and
one -RAS timing line. These four lines are used with an external 3-8
decoder to support eight banks of DRAM.
0 = -RAS encode disabled (default)
1 = -RAS encode enabled
6
MRA Enable
Enables the ‘‘Multiple RAS Active ’’ mode for higher system performance.
0 = Single RAS active mode (default)
1 = Multi RAS active mode. Also enables multiplexed DREQs
and encoded DACKs
5
RAM Disable
This bit disables the 82C836’s internal DRAM controller for accesses in
040000H-09FFFFH the range. 040000H-09FFFFH. These accesses are directed to the I/O
channel.
0 = Enables 040000H-09FFFFH DRAM range (default).
1 = Disabled 040000H-09FFFFH DRAM range.
4
High ROM
Enable
This bit should be set to one for PC/AT compatibility (see also ICR 46H
bit 5, high shadow RAM enable).
0 = Enable FC0000H and above (256K) as ROM (default)
1 = Enable FE0000H and above (128K) as ROM.
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