82C836 Datasheet, PDF (146/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s CPU Access to AT-Bus
System Timing Relationships
Maximum Wait State Page Miss
Figure 11-8 shows the fully-burdened local DRAM cycle i.e., the longest possible cycle
(eight T-states). It is a page miss cycle, meaning the target bank is the same as the
previously selected bank, but the row address must be changed. Thus, the same -RAS
signal must be cycled high and then low again.
• State T1 occurs only if the CPU ended the previous cycle in nonpipeline mode.
• Interval A is the Early Wait State, applicable only when internal EMS, Early READY
or LBA modes are enabled.
• Intervals B and C are needed for -RAS precharge time. For an encoded -RAS bank
switch, only B is needed. For -CAS only cycles, neither B or C is needed.
• Intervals D and E are the normal RAS, row/column and CAS sequence. Only E is
needed with CAS-only cycles.
• Interval F is the CAS Extend wait state (optional).
With the Early Wait State enabled, the minimum -CAS precharge time increases from
one PROCCLK cycle to three. With the CAS Extend wait state, the minimum -CAS
active time increases from two PROCCLK cycles to four. Neither type of wait states
affect the delay from -RAS to row address hold, or from column address valid to -CAS
active.
RAS timeout, if enabled, operates as follows:
• If -RAS remains low long enough to cause a RAS timeout (nominally 9.5
microseconds), the current memory cycle (if any) is allowed to finish, and then -RAS
is forced high at the middle of the next T-state after the end of the cycle.
• The -RAS that had been active remains high for a minimum of four PROCCLKs. If
an attempt is made to access the same bank again, the timing will follow either a page
miss or a bank switch sequence as needed to insure four PROCCLK cycles minimum
high time on -RAS.
• If access is made to a different bank, normal bank switch timing is followed.
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PRELIMINARY
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