82C836 Datasheet, PDF (126/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s Configuration Registers
82C386 CHIPSet Data Sheet
Table 10-18. Index 63H----High Performance Refresh (continued)
Bit
Name
Description
4-3
Hidden Refresh
Adjusts hidden refresh timing according to CPU speed. Refresh timing
Timing
during HLDA is not affected.
00 = Reserved
01 = 16MHz CPU speed (default)
10 = 20MHz or 25MHz CPU speed
11 = Reserved
2
Refresh Delay
Enables extra delay from one refresh to the next when an add-on card bus
master holds -REF active long enough to cause multiple back-to-back
refresh cycles. As in a PC/AT, refresh address remains the same for each
subsequent refresh cycle occurring while -REF remains continuously
asserted.
0 = One microsecond delay from -XMEMR active to next -XMEMR active
for multiple refresh in Master mode (default)
1 = No delay added; same timing as in revision 1.
Normally, this bit should remain zero to prevent subsequent refreshes
from starting prematurely when a Master keeps -REF asserted longer than
necessary for one refresh cycle (or when -REF has unusually long rise time
due to insufficient pull-up resistance).
1
----
Reserved. Write as 0.
0
Write Through
In cache-based SCATsx systems, memory writes normally go directly to
Disable
DRAM without any delay as compared to non-cache systems; local memory
writes cannot be ‘‘claimed ’’ by the cache controller. This bit changes
memory write protocol so that memory writes can be claimed by external
logic i.e., no write cycle performed in memory. In a cache-based system,
this feature generally will be useful only for diagnostic purposes. This
features may also be useful in certain high-performance, non-cache systems
that rely on dynamic cycle claiming on writes as well as reads.
0 = Normal write-through protocol (default); no early wait state
1 = Write-through disable; writes can be externally claimed; early wait state
inserted.
Only local memory writes are affected by this bit. Local memory reads and
all AT bus memory or I/O accesses are already subject to cycle claiming
(ICR 41H bits 5 and 6). If this bit is set to one, ICR 41H bit 5 or 6 (or both)
should also be set to one.
For timing reasons, hidden refresh mode of Index 63H requires that the CPU operate
exclusively in nonpipelined mode; the -NA signal to the CPU must be held high
continuously. The -NA output from SCATsx is not affected (if SCATsx is programmed
for -STCYC mode on the NA/STCYC pin, the -STCYC pulse is delayed until the hidden
refresh is complete).
The CPU address bus remains available to the CPU during hidden refresh, so AT bus
refresh must either be turned off (see bit 5 in ICR 63H) or the AT bus refresh address
must be provided by other external logic. The 82C835A cache controller is designed to
provide the AT bus refresh address during hidden refresh. SCATsx continues to generate
-REF and -XMEMR during hidden refresh if AT bus refresh is enabled, and the 82C835
can be programmed to use these signals to generate the AT bus refresh address.
1 0-1 4 Revision 3.0
PRELIMINARY
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