82C836 Datasheet, PDF (87/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

Interrupt Controller
Programming the Interrupt Controller s
Figure 7-11. ICW4----Address 021H (0A1H) Write Only
B7 B6 B5 B4 B3 B2 B1 B0
___________________________ ________ _________________ ________ ________
X
AEOI
X
EMI
X
Auto End-Of-Interrupt
Enable Multiple Interrupts
bits: B0
B1
X
AEOI
B2-B3 X
B4 EMI
B5-B7 X
This bit does not matter.
Auto End-Of-Interrupt is enabled when ICW4 is written with a zero
in both interrupts. The interrupt controller performs a non-specific
EOI on the trailing edge of the second INTA cycle. Note that this
function should not be used in a device with fully nested interrupts,
unless the device is a cascade master.
These bits are ignored.
Bit 4 enables multiple interrupts from the same channel in Fixed
Priority mode. This allows INTC2 to fully nest interrupts when
Cascade mode, with Fixed Priority mode, are both selected without
being blocked by INTC1. Correct handling of this mode requires the
CPU to issue a nonspecific EOI command to INTC2 and check its
In-Service Register for zero when exiting an interrupt service
routine. If zero, a nonspecific EOI command should be sent to
INTC1. If nonzero, no command is issued.
These bits are ignored.
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