82C836 Datasheet, PDF (82/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s End-Of-Interrupt
Interrupt Controller
Priority Assignment
Assignment of priority is based on an interrupt channel’s position relative to the other
channels in the interrupt controller. After the initialization sequence, IR0 has the highest
priority, IR7 has the lowest, and priority assignment is fixed (Fixed Priority mode).
Priority assignment can be rotated either manually (Specific Rotation mode) or
automatically (Automatic Rotation mode) by programming Operational Command
Word 2 (OCW2).
Fixed Priority Mode
This is the default condition that exists unless rotation (either manual or automatic) is
enabled, or the controller is programmed for Polled mode. In Fixed Priority mode,
interrupts are fully nested with priority assigned as shown in the following Figure.
Figure 7-4. Fixed Priority Mode
Lowest
Highest
Priority Status _{B7 B6 B5 B4 B3 B2 B1 B0}
Nesting allows interrupts with higher priorities to generate interrupt requests prior to the
completion of the interrupt in service. When an interrupt is acknowledged, priority is
resolved, the highest priority request’s vector is placed on the bus, and the ISR bit for that
channel is set. This bit remains set until an EOI (automatic or CPU generated) is issued
to that channel. While the ISR bit is set, all interrupts of equal or lower priority are
inhibited. Note that a higher priority interrupt that occurs during an interrupt service
routine, is acknowledged only if the CPU has internally re-enabled interrupts.
7-6 Revision 3.0
PRELIMINARY
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