82C836 Datasheet, PDF (158/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s CPU Access to AT-Bus
System Timing Relationships
Master Arbitration
Figure 11-15 shows how an add-on card bus master obtains, and later releases, control of
the buses. The general AT-compatible protocol is as follows:
• The Master asserts an assigned DREQ and waits for the corresponding -DACK, just
as in a DMA sequence. However, before a DMA channel can be used for Master
operation, software must program the channel for cascade mode. Then, when DREQ
is received for that channel, the 82C836 refrains from starting a DMA cycle after
issuing -DACK.
• Upon receiving -DACK, the requesting Master asserts the MASTER signal. This
reverses the directions of various bus drivers, forces AEN to be de-asserted, and
signifies that the Master is now in control.
• The Master can remain in control indefinitely, performing I/O or memory reads and
writes as needed. The Master releases control by deasserting -MASTER and DREQ.
Figure 11-15. Master Arbitration
Master read and write cycles on the AT bus follow the same basic protocol as CPU reads
and writes to the AT bus, except as follows:
• Address and command are controlled by the add-on card bus master and are not
necessarily synchronized to BUSCLK.
• ALE remains continuously high, and timing for UA17-23 is the same as the timing for
SA0-19.
• Data transfer is between the Master and an I/O resource, or between the Master and a
memory resource, using the same command signals as CPU controlled cycles.
1 1 -26 Revision 3.0
PRELIMINARY
Chips and Technologies, Inc.