82C836 Datasheet, PDF (92/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

s DMA Controller
DMA Controller
The DMA clock, internal to the 82C836, controls the DMA transfer rate and timing.
It is derived from the BUSCLK and is selectable as either BUSCLK/2 (default,
AT-compatible) or BUSCLK. Wait states during DMA operations are programmed
with internal configuration register 01H, bits 5-2. Refresh, which occurs at 15 µs
intervals (nominally), is determined by counting down the 1.19MHz (OSC1/12) clock.
The refresh period is set by programming timer channel 1 of the 8254 timer/counter.
Table 8-1 shows the usage of DMA levels on the I/O channel. The DMA requests are
shown by priority, starting with the highest level.
Table 8-1. DMA Request Levels for Each I/O Channel
DMA Level
DRQ0
DRQ1
DRQ2
DRQ3
DRQ4
DRQ5
DRQ6
DRQ7
System Board
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
I/O Channel
Available
Available
Diskette drive
Available
Available
Available
Available
Available
DMA cycle length control is provided internally in the 82C836 allowing independent
control for both 8-bit and 16-bit cycles. This is done through the programmable registers,
which can extend command signals or insert wait states.
Each DMA channel has a pair of 16-bit counters and a reload register for each counter.
The 16-bit counters allow the DMA to transfer blocks as large as 65,536 words. The
register, associated with each counter, allows the channel to reinitialize without
programming. The following description of the DMA subsystem pertains to both DMA1
and DMA2 unless otherwise noted.
Although the 8237 provides a ‘‘memory-to-memory ’’ mode of transfer, this 8237-
compatible mode is not usable in PC AT-compatible architectures, including SCATsx.
The memory-to-memory mode requires the use of the temporary data holding register in
the 8237, which is not accessible during DMA because of the way the bus buffers are
controlled. Furthermore, AT-compatible architectures, such as SCATsx, do not contain
steering logic to allow memory write data to come from the 8237 instead of an I/O
resource. It is possible that 8-bit memory-to-memory transfers might work successfully
anyway (accidentally) if there is sufficient bus capacitance to preserve the data between
the memory read cycle and memory write cycle, but this approach cannot be considered
reliable. Information concerning memory-to-memory transfer is included in this
datasheet only because the 82C836 implements the same 8237-compatible functionality
found in the PC/AT.
8-2 Revision 3.0
PRELIMINARY
Chips and Technologies, Inc.