82C836 Datasheet, PDF (187/205 Pages) List of Unclassifed Manufacturers – Single-Chip 386sx AT

System Characteristics
AC Characteristics 25MHz s
DMA and AT-Bus Master Access to Local Memory
The DMA and AT bus master access to local memory are shown in Tables 12-37
through 12-39.
Table 12-37. DMA and AT-Bus Master Access to Local Memory----Output Responses
Symbol
t230
t231
t232
t233
t234
t235
t236
t239
t240
t241
t242
Parameters
-RAS high from HLDA rise
A0-23 and -BHE float from -MASTER active
Command float from -MASTER active
-MWE rise from -XMEMR fall
-MWE fall from -CAS rise
-RAS inactive from -XMEMR or -XMEMW high
-CAS inactive from -XMEMR or -XMEMW high
-RAS active from XMEMR or XMEMW
A20 valid from MODA20 during MASTER access
A0 valid from MODA0 during MASTER
SDIRL, H fall from -XMEMW fall (Master Write)
* 35ns maximum for 82C836A.
Min.
Max.
----
50
----
60
----
30
----
40*
2
60
----
42
----
50
----
36
----
25
----
19
----
40
Table 12-38. DMA and AT-Bus Master Access to Local Memory----Formula Specifications
Symbol
te230
te233
te235
te239
te240
te242
Critical Path
RAS precharge before refresh
MWE rise before CAS fall (read)
RAS precharge, Master
Master read, access from RAS
Row address setup before RAS
Master write, SDIR fall
Formula
t230-t263-t265
t233-t102
t235-t239
t239+t145
t240-t239+t106
t242+t147
Max.
27
18
16
51
25
65
Table 12-39. DMA and AT-Bus Master Access to Local Memory----Input Requirements
Symbol
t250
t251
Parameters
PARL, PARH setup before -XMEMR rise during memory read
PARL, PARH hold after -XMEMR rise during memory read
Min.
Max.
20
----
0
----
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